Western Digital Technologies, Inc.

Arun Kumar Medapati

Ajith Kumar B

Ashwin Narasimha

Sri Rama Namala

Krishanth Skandakumaran

Sandeep Sharma

Ajith Kumar Battaje

Tanay Goel

Saurabh Manchanda

A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive a read request for a first translation table entry associated with a logical block, identify a dump unit associated with the logical block using a hash function, determine a dump group associated with the dump unit, and identify a second translation table entry associated with the dump unit.

Unified paging scheme for dense and sparse translation tables on flash storage systems

Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.

System and method for controlling PCIe direct attached nonvolatile memory storage subsystems

A storage device may include a non-volatile memory; and a controller. The controller may be configured to store a plurality of blocks of data in the memory, determine exclusive-or (XOR) parity data for the plurality of blocks, and store the XOR parity data in the memory; store a second block of data in the memory. The controller may be further configured to generate updated XOR parity data by at least XORing a first block of the plurality of blocks and the second block of data with the XOR parity data to remove the first block from the XOR parity data and to add the second block to the XOR parity data, and store the updated XOR parity data in the memory.

Updating exclusive-or parity data

A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a first translation table entry for a logical block, map the first translation table entry to a first dump unit, the first dump unit included in an array of dump units, identify a second translation table entry for the logical block in the first dump unit, the second translation table entry also being stored in a storage device, and generate a linked list in the storage device from the second translation table entry associated with the first dump unit, the linked list identifying previous translation table entries associated with the logical block.

Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.

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Andhra Pradesh, India

Arun Kumar Medapati