Synopsys, Inc.

Arun Kumar

Yervant Zorian

Gurgen Harutyunyan

Karen Darbinyan

Grigor Tshagharyan

Mher Mkhoyan

A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.

Built-in self-test circuit for row hammering in memory

A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.

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Santa Clara, CA, United States of America

Arun Kumar