Genesis Microchip Corporation

Chips and Technologies, Llc.

Sage, Inc.

Chips and Technology, Inc.

Arun Johary

Hari N Nair

Neha Agrawal

Saif Choudhary

Sandeep Agarwal

Tetsuji Oguchi

Ashish Neema

Morris E Jones, Jr

Shashi Kumar

Mark A Rosenau

Pierre M Selwan

Edward P Hutchins

Mahesh Siddappa

David G Reed

An apparatus and method for allowing color adjustments in display devices is disclosed The apparatus comprises a multi-resolution structure for providing color adjustments; and an interpolator for interpolating at least one offset of the multi-resolution structure. An apparatus and method in accordance with the present invention uses a combination of color look-up tables with different levels of resolution, followed by interpolation to provide a display process which has high resolution but utilizes minimal memory. In so doing, memory is used for high-resolution areas only where needed. The multi-resolution structure is a very good approximation to the theoretical mapping table in the areas where it is needed. At the same time, since the high resolution areas are localized, a significant reduction in memory storage is possible.

Apparatus and method for multi-resolution color mapping for display devices

A method and apparatus that allows a display device to adaptively and automatically control display contrast and color is disclosed. The method and system in accordance with the present invention can be described by the following sequential process:

Method and system for adaptive color and contrast for display devices

Automatically and adaptively controlling contrast and color of a display device by computing a normalized histogram of a current image, computing degrees of correlation between the normalized histogram and a number of template histograms, sorting the template histograms based upon the associated degrees of correlation, selecting a number of the best correlated template histograms based on the sorting, blending the selected the transfer functions associated with the selected template histograms to form a blended transfer function, and applying the blended transfer function to the current image.

Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display

A method and system for scaling an image in accordance with the present invention is disclosed. The method utilizes a plurality of interpolators operating in parallel. Each interpolator operates with a different spatial offset with respect to the other. The final output is the average the output of each interpolator. Normally the initial value of the horizontal and vertical DDA's is zero. Offset is introduced by introducing an initial value in the DDA. Offset has the physical effect of manipulating the weights required for the averaging process in interpolation. Horizontal offset is the initial value in the Horizontal DDA while the vertical offset is the initial value in the Vertical DDA. The present invention relates to implementation in a semiconductor integrated circuit but the concepts can be used in software based image resizing (scaling) algorithms too.

Method and system for dual spatial or temporal scaling

Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.

Method and apparatus for performing run length tagging for increased

A method and apparatus for improving the quality of a color-to-gray scale conversion is disclosed. A table is generated providing a visually correct conversion of all possible background/foreground colors. This table is then stored. In operation, after the attribute byte describing the foreground and background colors is retrieved from memory, it is used to access the stored conversion table, wherein its gray scale equivalent is stored. The stored equivalent is then used to generate the gray scale LCD display. In other embodiments, multiple copies of the table are stored, making multi-frame operations very efficient in operation.

Method and apparatus for improved color to monochrome conversion

A video display controller capable of providing video control information for either a flat panel or a CRT display. The controller includes a plurality of main circuits, alternate circuits, select circuits, and a circuit for identifying the display device used in the system. Each main circuit receives information from the processor and generates main video information compatible with a CRT. Each alternate circuit receives information from the processor and generates alternate video information compatible with a flat panel display. Each select circuit receives main and alternate video information and outputs main video information when the display device is a CRT display and the alternate video information when the display device is a flat panel display. In one embodiment, the alternate circuits are programmable registers. In another embodiment, tables are used to program the alternate registers to provide compatibility for a number of possible display devices.

Fakeout method and circuitry for displays

A controller for providing O to N gray scales at a monochrome display. The monochrome display is of the type having an array of pixels energized by a display voltage over time to generate the gray scales. The controller generates a baseline time and uses the baseline time to provide gray scales at the display. In particular, each pixel is energized at least the baseline time for any gray scale above level 0 to reduce flicker in the display. In one embodiment, the baseline time corresponds to a point on the intensity response curve for the display at which the display exhibits a linear intensity response for a given display voltage versus time. In one embodiment, the baseline time is used to generate pixel on/off data to provide gray scales at the display. In yet another embodiment, the baseline time information is used to generate weighted clock information to provide gray scales at the display. In another aspect, the controller includes a plurality of programmable gray scale generators which provide pixel on/off data, weighted clock information, and black/white pixel data to provide gray scales at the display. One of the gray scale generators is selected and programmed depending on the identity of the display device.

Gray scales method and circuitry for flat panel graphics display

A method and apparatus for scaling interlaced video data allows the video data to be scaled to any desired size, either larger or smaller than the original image. The method considers each line of input data in each field sequentially, and determines whether the line is to be saved and whether the data lines in each successive field will also be saved, discarded, or duplicated, saving space in the output buffer for the saved and duplicated data lines to come as necessary. The method can accommodate interlaced data with N field and a scaling factor M.

Method and apparatus for scaling interlaced images

A method and apparatus for scaling interlaced video data allows the video data to be scaled to any desired size, either larger or smaller than the original image. The method considers each line of input data in each field sequentially, and determines whether the line is to be saved and whether the data lines in each successive field will also be saved, discarded, or duplicated, saving space in the output buffer for the saved and duplicated data lines to come as necessary. The method can accommodate interlaced data with N field and a scaling factor M. An apparatus for implementing the method for two header fields and scaling factor N is also described.

A data processing system includes a video controller and a flat panel display system. The flat panel display system includes first and second flat panel displays adapted so as to appear to be essentially a single display. The video controller includes a first and second address generator for generating first and second address information and a counter for counting vertical sync position to identify alternating first and second display frames. The controller outputs the first address information to drive the first display and the second address information to drive the second display during the first display frames and outputs the second address information to drive the first display and the first address information to drive the second display during the second display frames. The displays are identical and the address generators are identical. The use of dual displays with dual, flip-flopping address generators is more advantageous than using a single address generator to drive two display panels.

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San Jose, CA, United States of America

Arun Johary