Qualcomm Incorporated

Conexant Systems, Inc.

Tripath Technology, Inc.

Fairchild Semiconductor Corporation

Integrated Device Technology, Inc.

Northwestern University

Rehabilitation Institute of Chicago

Arun Jayaraman

John A Rogers

Cary L Delano

Gurkanwal Singh Sahota

Bo Sun

Gary John Ballantyne

Sandip HomChaudhuri

Brian Ben North

Sankaran Aniruddhan

Shuai Xu

Kun Hyuck Lee

Jason Alexander Young

Angela Roberts

Megan O'BRIEN

Leora Cherney

Edna Babbitt

Bonnie Martin-harris

Xiaoyue Ni

Systems, methods, and devices for saving power in wireless communications devices are described herein. In some aspects, an apparatus includes a memory unit configured to store wake-up information associated with a wake-up time duration for receiving a beacon signal, and includes a processor operationally coupled to the memory unit. The wake-up time duration identifies a time for the processor to wake-up before an expected arrival time of the next beacon signal. The processor may be configured to retrieve the wake-up information from the memory, and vary, over a period of time, the wake-up time duration based on the wake-up information.

Dynamic selection of early-RX duration during network sleep operation

A system and method for efficient computation in the course of locating a position on the face of a touch-screen-equipped display device by limiting the amount of computations to weighted vectors within a range substantially less than the entire range of data input from the touch screen sensors.

Electronic display with array context-sensitive search (ACS) technology

A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.

Mixer with high output power accuracy and low local oscillator leakage

A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier.

Bi-polar modulator

This disclosure describes designs for a digitally controlled oscillator (DCO). The DCO can overcome many of the shortcomings associated with conventional voltage controlled oscillators (VCOs), and may improve wireless communication devices. The described DCO may improve the frequency synthesis process, reduce noise in a wireless communication device, and allow for simplification of various components of the device.

High resolution digitally controlled oscillator

An efficient class-G amplifier having multiple rails is configured with parallel class AB amplifiers powered by at least one rail supplying a voltage that can be varied in response to signal characteristics, typically as sensed at an output across a load. In a specific embodiment, an analog-to-digital converter is coupled to a digital signal processor that converts signals into a programmed voltage level for setting the voltage rail.

Adaptive rail amplifier (ARA) technology

A system and method for designing a broadband tuner such that VCO pulling is minimized and gaps in frequency coverage are avoided, while total power consumption is reduced, is disclosed. A broadband spectrum is divided into sub-bands and various multipliers to a local oscillator output are introduced. In this fashion, the present invention allows a local oscillator within the broadband tuner to always generate signals that lie outside of the broadband spectrum for a particular broadband application. Additionally, a modulus ratio for a dual modulus prescaler with the local oscillator is maximized, thereby reducing power consumption.

System and method of frequency synthesis to avoid gaps and VCO pulling in direct broadcast statelite systems

System and method of frequency synthesis to avoid gaps and VCO pulling in direct broadcast satellite systems

A bandpass amplifier for use in a communication system is described. The amplifier includes a frequency selective network having a feedback path. The frequency selective network has first filtering circuitry for selectively passing the transmit band, and second filtering circuitry for selectively passing the receive band. The first filtering circuitry and the second filtering circuitry pass frequencies in the transmit band and reject frequencies in the receive band. A sampling analog-to-digital converter is coupled to the frequency selective network. A switching device is coupled to the sampling analog-to-digital converter for producing a continuous-time output signal. A feedback path is provided for continuously sensing and feeding back the continuous-time output signal to the frequency selective network.

Receive band rejection for a digital RF amplifier

A bandpass amplifier for use in a communication system is described. The amplifier includes a filter, a quantizer, a driver, and a feedback loop. The filter filters the input signal, thereby generating a filtered signal. The quantizer quantizes the filtered signal into one of two values, thereby generating a quantized signal. The driver amplifies the quantized signal, thereby generating the output signal. The feedback loop feeds the output signal to the filter. The quantizer has characteristics in which the quantized signal does not fluctuate between the two values when the input signal is substantially stable.

Scheme for maximizing efficiency of power amplifier under power backoff conditions

A bandpass amplifier for use in a communication system is described. The amplifier includes first and second first-order filters, first and second multipliers, a quantizer, and a driver. In one embodiment, the first and second first-order filters are coupled in series. The first multiplier multiplies a signal from the first first-order filter by a coefficient k1, and the second multiplier multiplies a signal from the second first-order filter by a coefficient k2. The quantizer quantizes a summation of the signals from the first and second multipliers into one of two values, thereby generating a quantized signal. The driver amplifies the quantized signal, and generating an output signal. At least one of the coefficients k1 and k2 is adjusted based on a level of the output signal.

Scheme for reducing transmit-band noise floor and adjacent channel power with power backoff

A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a master-slave flip-flop. An input clock signal having a frequency FN is supplied to the flip-flop of each circuit block, and an output clock signal having a frequency FN/2 or FN/3 is generated in response. A control signal supplied to the OR gate of the second circuit block determines whether the frequency will be divided by 2 or by 3. The circuit blocks generate differential output signals, and common-mode signals are generated for supply to the OR gate inputs by summing and dividing the differential output signals with high value resistors.

Growing community of inventors

San Diego, CA, United States of America

Arun Jayaraman