Sun Microsystems, Inc.

Arun Chandra

Marcelino M Dignum

Daniel L Liebholz

Manish Singh

Vivek D Sagdeo

A method and apparatus for improved formal equivalence checking to verify the operation of components in a VLSI integrated circuit. The present invention enhances previous techniques for dynamic circuits by generating a multi-level transistor abstraction for dynamic circuits. Two-levels of abstracted code are generated. First, an abstracted legal Verilog&#xae; is generated for the evaluate phase of a dynamic circuit. Second, 'comment-logic' in Verilog&#xae; syntax is generated for the pre-charge phase of the dynamic circuit. Using the method and apparatus of the present invention, it is possible to obtain a multi-level transistor abstraction for both the 'clk=0' and the &#x201c;clk=1&#x201d; conditions. The binary decision diagram property of the circuit being analyzed is used to generate multi-level representations for both the pre-charge (clk=0) and the evaluate phases (clk=1). The multi-level abstracted model of the present invention has several advantages over the prior art. The legal Verilog&#xae; can be used for traditional simulation and equivalency verification, ATPG. The &#x201c;comment logic&#x201d; can be used with a property checking tool to verify that the clock connectivity is correct. In addition, the present invention has the advantage of being able to generate legal Verilog&#xae; with pre-charge for verification against RTL with detailed pre-charge information.

Multiple level transistor abstraction for dynamic circuits

A method for comparing two delimited strings, each of which has a plurality of substrings, includes pairing each substring in one of the delimited string with a corresponding substring in the other one of the delimited strings. The method further includes computing a proximity value for each pair of substrings, and computing a set of decaying weights corresponding to the pairs of substrings, multiplying the proximity value for each pair of substrings by the corresponding weight, and summing the weighted proximity values to obtain a strength of match between the delimited strings.

Approximate string matcher for delimited strings

A method for constructing a latch mapping between a first level description and a second level description of a digital system, wherein the first level description and the second level descriptions identify components in the digital system using a predefined naming convention, is provided. The method includes identifying first latch components in the first level description and, for each identified first latch component, storing a first string comprising a selected property of the first latch component in a first storage. The method further includes identifying second latch components in the second level description and, for each second latch component, storing a second string comprising a selected property of the second latch component in a second storage. The method further includes generating a latch mapping by matching the first strings in the first storage with the second strings in the second storage.

Growing community of inventors

Cupertino, CA, United States of America

Arun Chandra