Nec Usa, Inc.

Other

Nec Corporation

Lsi Logic Corporation

Nec Electronics Corporation

Arun Balakrishnan

Srimat T Chakradhar

Jun Qian

Anand Raghunathan

Wolfgang Roethig

Ganesh Lakshminarayana

Kaushik De

A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU times are provided. Scan memory elements are selected so that the scanned circuit satisfies two key properties in the test mode. First, the scanned circuit has partitions that are peripherally interacting finite state machines (peripheral partitions). Second, the memory element dependency graph (S-graph) of each peripheral partition of the scanned circuit has a tree structure. An efficient for algorithm peripheral partitioning and tree decomposition is provided. The scan memory element selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure.

Peripheral partitioning and tree decomposition for partial scan

The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.

Multi-level power macromodeling

A system and method for representing a system level RTL hardware design using an HDL independent RTL representation and translation into synthesizable RTL code. The present invention creates an object-oriented library which can be used to implement RTL hardware designs in terms of HDL independent objects. Instead of implementing multiple HDL instances of hardware modules, the invention enables software tool programmers to implement one HDL-independent instance of the hardware module. As a result, a programmer can focus his efforts on generating the functionality of the module and can be relieved from the time consuming task of generating the detailed syntax of multiple HDLs. The present invention also maintains synchronization across multiple HDLs so that a software designer can generate HDL code for any supported HDL, e.g., Verilog or VHDL, thus making software maintenance easier.

System and method for representing a system level RTL design using HDL

A process for generating a test set for a sequential integrated circuit that includes performing a transformation on a software model of the circuit to provide a modified software model that should be more easily tested but that need not be functionally equivalent, and deriving a test set for the modified software model in conventional fashion. Thereafter, the derived test set is inverse mapped to derive a test set for the original sequential circuit. The transformation used essentially involves (1) the borrowing and/or returning registers at the primary inputs and/or primary outputs and (2) positioning the registers in the modified model as needed.

Test generation of sequential circuits using software transformations

Growing community of inventors

Santa Clara, CA, United States of America

Arun Balakrishnan