Sk Hynix Nand Product Solutions Corp.

Arun Athreya

Shankar Natarajan

Yihua Zhang

Shivashekar Muralishankar

Sriram Natarajan

Parth Donga

Mariusz Dolny

Bartosz Kot

Michal Mamczyński

Michał Mamczyński

Orapin Yoder

A system and related method, including system memory with a source memory block and a destination memory block each of a memory block size, a first volatile memory and a second volatile memory, each of a volatile memory size. The system includes processing circuitry to receive a garbage collection request associated with the destination memory block. The processing circuitry then determines whether the memory block size is greater than the volatile memory size and pauses data change operations but allows for passive operations to continue. While data change operations are paused the processing circuitry loads a first portion of data of the source memory block to the first volatile memory and a second portion of the data to the second volatile memory. The processing circuitry writes each portion of data from the volatile memory to the destination memory block to complete garbage collection and unpauses the data change operations.

System and methods for DRAM-less garbage collection with improved performance

A system and related method, the system including control circuitry and memory with a first memory block of a first memory density and a second memory block of a second memory density which is greater than the first memory density. Control circuitry, which is communicatively coupled to the memory, is configured to determine to transfer data from the first memory block to the second memory block, generate parity data based on the data and cause to store the parity data at a parity address corresponding to an available portion of the first memory block. Control circuitry is further to cause to update a look-up table with the parity data address and cause to copy the data from the first memory block to the second memory block.

Flexible raid parity application for memory management

A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.

Methods and systems for software based prefetching for low buffer depth sequential read traffic

This application is directed to data protection in a memory system of an electronic device. The memory system has a first memory block and a second memory block, and each memory block includes one or more respective memory dies. Each memory die of the second memory block is distinct from the one or more respective memory dies of the first memory block. The electronic device stores user data including a plurality of user data items in the first memory block and integrity data including a plurality of integrity data items in the second memory block. Each of the plurality of user data items is configured to be validated based on a respective one of the plurality of integrity data items. The electronic device invalidates the integrity data in the second memory block, and reads the user data from the first memory block independently of the integrity data.

Controlling memory overhead for storing integrity data in solid state drives

Growing community of inventors

Folsom, CA, United States of America

Arun Athreya