Xilinx, Inc.

Arun Ananthapadmanaban

Venkata V Dhanikonda

A video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block. The buffer is capable of receiving and storing a video signal as video data. The packetizer block is capable of packetizing video data read from the buffer and sending packetized data to a node external to the video processing system. The buffer controller is capable of controlling an amount of video data included within each packet generated by the packetizer block.

Reducing artifacts within a video processing system using a buffer management system

An embodiment of a video processing system can include an alignment detector block configured to determine whether a video signal is misaligned and, responsive to determining that the video signal is misaligned, generate notifications indicating misalignment of the video signal. The video processing system also can include an unlock detector block coupled to the alignment detector block that is configured to determine an amount of time that the video signal is misaligned according to the notifications from the alignment detector block. The unlock detector block can be configured to ignore misalignment of the video signal until the video signal is misaligned for an amount of time exceeding a threshold amount of time. Another embodiment of the video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block.

Growing community of inventors

Hyderabad Telangana, India

Arun Ananthapadmanaban