Spansion Llc.

Arturo Ruiz

Ning Cheng

Huaqiang Wu

Jihwan Choi

Hiro Kinoshita

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.

Growing community of inventors

San Jose, CA, United States of America

Arturo Ruiz