Ip-first, LLC

International Business Machines Corporation

Other

Integrated Device Technology, Inc.

Arturo Martin-de-Nicolas

G Glenn Henry

Terry J Parks

Gerard M Col

James Allan Kahle

Gary Douglas Huber

Soummya Mallick

Dinesh K Jain

Thomas A Crispin

Seungyoon P Song

Albert J Loper, Jr

Daniel G Miner

John D Bunda

Ronald S Harter

A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.

Microprocessor including random number generator supporting operating system-independent multitasking operation

The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and execution logic. The cryptographic instruction is received by a computing device as part of an instruction flow executing on the computing device, wherein the cryptographic instruction prescribes one of the cryptographic operations. The execution logic is operatively coupled to the cryptographic instruction and executes the one of the cryptographic operations. The one of the cryptographic operations includes indicating whether the one of the cryptographic operations has been interrupted by an interrupting event.

Apparatus and method for performing transparent block cipher cryptographic functions

An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus, and translates each of the macro instructions into associated native instructions for execution. If a first form of a first macro instruction is retrieved, the instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register. The bypass logic is coupled to the instruction translation logic. The bypass logic accesses the first bit within the control register to determine if the native bypass mode has been enabled, and detects wrapper macro instructions and, upon detection of the wrapper macro instructions, disables the instruction translation logic, and provides the native instructions for execution by the microprocessor, thereby bypassing the instruction translation logic.

Mechanism in a microprocessor for executing native instructions directly from memory

An apparatus and method are provided for combining multiple instructions prescribing accesses to a microprocessor stack into a single micro instruction. The apparatus includes a translator and access alignment logic. The translator receives a first stack access instruction and a second stack access instruction from an instruction queue, and decodes them into an associated micro instruction directing the microprocessor to accomplish both accesses prescribed by the stack access instructions during a combined access, wherein the combined access is achieved in a single instruction cycle. The access alignment logic is coupled to the translator and indicates alignment of two data entities within a cache for the combined access. The two stack access instructions are not combined when the access alignment logic indicates that the combination of the data entities is misaligned within the cache.

System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution

An apparatus and method are provided for executing a push all/pop all instruction in a pipeline microprocessor. The apparatus includes an instruction buffer and a translator. The instruction buffer provides the push all/pop all instruction, directing the microprocessor to store/retrieve multiple operands to/from a stack. The translator generates a sequence of micro instructions to store/retrieve the multiple operands. Accesses to a pair of operands which are together aligned are combined into a single access.

Apparatus and method for optimizing execution of push all/pop all instructions

A method for improving the execution of significant bit scans on a data entity in a computer system is provided. The data entity is examined in a number of iterations equal to the base two logarithm of the size of the data entity in bits, N. Initially, half of the data entity is examined to determine if the significant bit is present. If not, the other half of the data entity is examined. The half within which the significant data entity resides is then iteratively halved and examined in each successive iteration of the method until the number of bits examined is equal to one.

Method for improved bit scan by locating a set bit within a nonzero data

An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Concurrent execution of divide microinstructions in floating point unit

An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and logically merges the fuse states with a default configuration for the functional blocks. The result of the merge operation is stored in a feature control register that individually enables/disables the functional blocks. The control unit also receives a write command from an external source that modifies the feature control register, after the device is shipped from the manufacturer. The control unit selectively blocks writes to the feature control register that attempt to enable/disable functional blocks that should not modified.

Fuse array control for smart function enable

A system and method for performing an emulation context switch save and restore in a processor that executes host applications and emulates guest applications. The processor includes an operating system and a first register that is saved and restored by the operating system during a host application context switch. The method and system comprises renaming the special-purpose register to the first register when emulating guest applications. When an emulation context switch occurs, a context save and restore of the special-purpose register is performed through the first register without operating system modification.

Method and system for performing an emulation context save and restore

The present invention provides a method and system for using hardware to assist software in emulating the guest instructions. The method and system comprises an emulation assist unit (EAU) which efficiently maps a guest instruction to a unique tag, an index, and an address of the corresponding semantic routine. The index determines where in a cache a plurality of tags are stored. A separate cache within the EAU stores each tag in association with the address the first time the corresponding guest instruction is emulated. Thus, the emulation assist unit also dynamically responds to the set of guest instructions being emulated. The first time a guest instruction is emulated, the EAU determines the address and stores the address in the cache in association with the tag. When the guest instruction is emulated again, the EAU uses the tag to access the stored addresses of the corresponding semantic routine.

Growing community of inventors

Austin, TX, United States of America

Arturo Martin-de-Nicolas