Cadence Design Systems, Inc.

Artur Melo Mota Costa

Fabiano Cruz Peixoto

Andrea Iabrudi Tavares

Alberto Manuel Arias Drake

Lawrence Loh

Breno Rodrigues Guimaraes

Tulio Paschoalin Leao

Paula Selegato Mathias

Guilherme Seminotti Braga

Rodrigo Fonseca Rocha Soares

Laiz Lipiainen Santos

Regina Mara Amaral Fonseca

Gabriel Guedes De Azevedo Barbosa

Tales Bontempo Cunha

Tamires Vargas Capanema Franco Santos

Lucas Ferreira De Melo Diniz

Rogério De Souza Moraes

Nathália Peixoto Reis

Patricia Sette Câmara Haizer

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.

Systems and methods for command interpretation in an electronic design automation environment

The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.

Systems and methods for automatic formal metastability fault analysis in an electronic design

Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

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Belo Horizonte, Brazil

Artur Melo Mota Costa