Intel Corporation

Artour Levin

Naresh K Sehgal

Iksoo Pyo

Miles F McCoo

Kiran Ganesh

A 2-dimensional placement system and method minimize reliability concerns arising from electromigration and self-heat while at the same time achieving a high layout density. The 2-dimensional placement method also uses a placement space with rows that have non-uniform sizes and are overlapping. According to one embodiment of the present invention, a computerized method of creating a layout for a circuit design includes receiving a circuit design and receiving at least one layout rule based on a reliability verification constraint for the circuit design. The computerized method further includes generating a layout for the circuit design through computer automated operations wherein the layout generated satisfies the at least one layout rule based on the reliability verification constraint received for the circuit design.

2-dimensional placement with reliability constraints for VLSI design

A method and system for generating resistance, capacitance and delay table look-ups for cell routers and placers is disclosed. The system receives statistical data describing a new net as well as a desired level of accuracy. One or more preexisting net models are divided into one or more groups, wherein the number of groups is associated with the desired level of accuracy. The system returns a table of coefficients associated with the statistical data and the one or more groups.

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San Jose, CA, United States of America

Artour Levin