National Semiconductor Corporation

Arthur Smith, Jr

Benjamin S Ting

Frederick Furtek

Scott K Pickett

Rafael C Camarota

David Warren Hawley

Sanjay Popli

Tim Garverick

Jim Sutherland

Shao-Pin Chen

Shankar Moni

Venkata Alturi

Shin-Mann Day

The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a plurality of logic cell I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix. Furthermore, the array includes a plurality of express bus I/O pins directly connectable to the express busses.

Direct I/O access to express bussing in a configurable logic array

A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.

Versatile and efficient cell-to-local bus interface in a configurable

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San Carlos, CA, United States of America

Arthur Smith, Jr