Western Digital Technologies, Inc.

Arthur Shulkin

David Rozman

Tomer Tzvi Eliash

Eran Sharon

Alexander Bazarsky

Ariel Navon

Dudy David Avraham

Stella Achtenberg

Alexander Kalmanovich

James Yin Tom

Systems and methods are described for predicting an endurance of groups of memory cells within a memory device, based on current characteristics of the cells. The endurance may be predicted by processing historical information regarding operation of memory devices according to a machine learning algorithm, such as a neural network algorithm, to generate correlation information between characteristics of groups of memory calls at a first time and an endurance metric at a second time. The correlation information can be applied to current characteristics of a group of memory cells to predict a future endurance of that group. Operating parameters of a memory device may be modified at a per-block level based on predicted block endurances to increase the speed of a device, the longevity of a device, or both.

Identifying memory block write endurance using machine learning

Systems and methods are described for reducing error rates on data storage devices by applying data shaping to data written to such devices in order to avoid error-prone states on cells within the devices. Different states of individual cells (such as those representing different bit patterns) may have different propensities for error, and these propensities may vary during operation of a device. Thus, a device as disclosed herein may determine error-prone states for a cell or group of cells, and apply data shaping to data written to such cells to reduce the likelihood that writing the data places the cell or cells into an error-prone state. Data shaping may be used, for example, to increase the occurrence of '0' bits within input data, thus avoiding error-prone low voltage states that may be used to represent a series of '1' bits.

Data shaping to reduce error rates in solid state memory devices

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period and manage the set of non-volatile memory cells according to a probability of occurrence of a target FBC in a second time period that is subsequent to the first time period. The probability of occurrence of the target FBC during the second time period is calculated from a model of FBC distribution change of the set of non-volatile memory cells.

Non-volatile storage with wear-adjusted failure prediction

Disclosed is a system and method for adjusting read levels in a storage device based on bias functions. The method includes receiving a request to perform a memory access operation on a wordline of non-volatile memory. The method also includes selecting a bias function corresponding to the wordline of the non-volatile memory from a group of bias functions. The method also includes determining a bias value based on the selected bias function and the wordline. The method also includes adjusting a read level in the non-volatile memory based on the bias value. The method also includes performing the memory access operation on the wordline of the non-volatile memory using the adjusted read level. The bias functions may be linear functions and adjusted in response to detecting a recalibration condition.

System and method for adjusting read levels in a storage device based on bias functions

Systems and methods are described for predicting potential failures in flash memory devices by probing for memory cells with marginal programming characteristics. A method includes receiving a write request. The method also includes applying a predetermined number of programming pulses to a plurality of memory cells within a block of a flash memory device. The method also includes applying a verify pulse to each respective one of the plurality of memory cells. The method also includes storing programming status of the plurality of memory cells into a set of latches. The method also includes determining, based on the stored programming status, a total number of memory cells within the block that fall outside of one or more predetermined expected ranges. The method also includes identifying the block as a block in risk when the total number of memory cells satisfies a predetermined risk threshold.

Failure prediction by cell probing

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells, obtain one or more metrics of a cumulative distribution of the FBCs, calculate an indicator from the one or more metrics of the cumulative distribution of the FBCs and a target FBC, obtain a probability for the target FBC from the indicator, and manage at least one of: garbage collection, wear leveling, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability for the target FBC.

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Yavne, Israel

Arthur Shulkin