Synopsys, Inc.

Facebook Technologies, LLC

Arthur Nieuwoudt

Alexander Sorkine Hornung

Alexandru-Eugen Ichim

Gaurav Chaurasia

Mathew Koshy

Baribrata Biswas

Arindam Chatterjee

Jiyoun Kim

Gioacchino Noris

Jan Oberländer

Matthew James Alderman

Gian Diego Tipaldi

William Patrick Pinello

Lingwen Gan

Beifang Qiu

Mathieu Eric Drut

Paul Timothy Furgale

Eldad Yitzhak

Alexei Svizhenko

Claude Helmstetter

In one embodiment for generating passthrough, a computing system may access images of an environment captured by cameras of a device worn by a user. The system may generate, based on the images, depth measurements of objects in the environment. The system may generate a mesh covering a field of view of the user and then update the mesh based on the depth measurements to represent a contour of the objects in the environment. The system may determine a first viewpoint of a first eye of the user and render a first output image based on the first viewpoint and the updated mesh. The system may then display the first output image on a first display of the device, the first display being configured to be viewed by the first eye of the user.

Systems, methods, and media for generating visualization of physical environment in artificial reality

In one embodiment, a method includes displaying, through a head-mounted display (HMD), virtual objects to a user wearing the HMD. The method then accesses a boundary definition that corresponds to a boundary within a physical space surrounding the user and generates a plurality of spatial points based on depth measurements of physical objects within the physical space. Based on the spatial points, a location at which a physical object is likely to exist is determined. The method determines whether the location of the physical object is inside the boundary definition and, in response to this determination, issues an alert to the user.

Systems and methods for detecting intrusion while in artificial reality

A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.

Determining ECO aggressor nets during incremental extraction

A method for floating node reduction uses a capacitance matrix that specifies coupling capacitances between signal nodes and floating nodes of an interconnect structure. Random walks are performed from a first signal node to the other signal nodes, wherein each of the random walks traverses one or more of the floating nodes. Each of the random walks is directed based on probabilities derived from the coupling capacitances of the capacitance matrix. A count is maintained for each of the other signal nodes, wherein each count specifies a number of the random walks that end on the corresponding signal node. The indirect coupling capacitance from the first signal node to a second signal node is selected to correspond with the total indirect coupling capacitance of the first signal node, times the count associated with the second signal node, divided by the total number of random walks.

Floating node reduction using random walk method

A parasitic-aware blockage structure is provided to replace a detailed blockage structure for use in connection with a capacitance extraction operation. The parasitic-aware blockage structure includes one or more parasitic-aware blockage polygons, each representing a plurality of polygons of the detailed blockage structure. The parasitic-aware blockage polygons can be formed by expanding and merging the polygons of the detailed blockage structure. Physical information is associated with each of the parasitic-aware blockage polygons, wherein the physical information defines physical characteristics of the polygons of the detailed blockage structure. Capacitance error information may also be associated with each of the parasitic-aware blockage polygons, specifying capacitive errors of the parasitic-aware blockage polygons with respect to the polygons of the detailed blockage structure.

Parasitic-aware blockage

A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying.

Capacitance extraction for advanced device technologies

A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

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San Carlos, CA, United States of America

Arthur Nieuwoudt