Texas Instruments Corporation

Arthur M Wilson

Robert H Taylor

Bruce E Gnade

Kenneth G Vickers

Juanita G Miller

Dean L Frew

Chi-Cheong Shen

Charles E Primm

Mark A Kressley

James M Drumm

Philip E Hecker, Jr

Richard A Elder

Wei-Yan Shih

Willmar E Subido

Clyde R Fuller

Randall E Johnson

Susan V Bagen

Prabhakar Bhimrao Ghate

Rick Elder

Charies E Primm

John E Hanicak

Saroja Ramamurthi

Stephen M Davis

David W Laks

Jody D Larsen

Randy Johnson

A device having a thin metallic coating, such as tin which forms strong bonds to copper is provided on the bond pads of an integrated circuit having copper metallization; surface oxidation of the coating is self limiting and the oxides are readily removed, further the coated bond pad forms intermetallics at low temperatures making it both solderable and compatible with wire bonding. A low cost process for forming tin coated copper bonding pads is provided by electroless plating.

Bonding pads for integrated circuits having copper interconnect metallization

An embodiment of the instant invention is a method of fabricating a semiconductor device with a patterned dielectric layer having an upper surface and an opening with a bottom and sidewalls formed over a semiconductor substrate, the method comprising the steps of: forming a liner layer (layer,of FIGS.,) on the upper surface of the patterned dielectric layer and on the bottom and the sidewalls of the opening in the patterned dielectric layer; forming a conductive layer (layer,of FIGS.,) on the liner layer; removing the portion of the conductive layer which overlies the top surface of the dielectric layer thereby exposing a portion of the liner layer while leaving the portion of the conductive layer situated in the opening of the dielectric layer substantially unremoved, the step of removing the portion of the conductive layer is accomplished by chemical mechanical polishing using a first slurry; removing the exposed portion of the liner layer while leaving the unexposed portion of the liner layer substantially unremoved by chemical mechanical polishing using a second slurry; and wherein the first slurry removes the conductive layer much more readily than the liner layer and the second slurry removes the liner layer more readily than the conductive layer.

Selective slurries for the formation of conductive structures

A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.

Method of forming a lift-off layer having controlled adhesion strength

An electron emitter plate (10, 10') for an FED image display has a gate conductive layer (22) spaced by a dielectric insulating layer (25) from a cathode conductive layer formed into a mesh (18). Arrays (12) of microtips (14) are located within mesh spacings (16) for field emission of electrons toward a phosphor layer (34) of an anode plate (11). Cathode layer (18) is patterned into column stripes (19) separated by gaps (17). Gate layer (22) is patterned into row cross-stripes (24) separated by gaps (23) which intersect with stripes (19) at matrix addressable pixel locations (30). Resistive layer (15) is patterned into stripes (40) separated by gaps (42) which interrupt column-to-column electrical communication through resistive layer (15). Unetched strips (43) are provided to bridge gap discontinuities for deposition of gate layer (22) at crossovers of rows (24) between columns (19). In one embodiment, gate layer (22) has a mesh pattern with apertured pads (46) commonly connected along resistive gap edges by marginal buses (50) formed on borders (49) of resistive layer (15) along gaps (42). Adjacent marginal buses (50) are connected by crossover buses (52) formed over bridging strips (43).

Column-to-column isolation in fed display

A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate. Electrical components are applied to the region of first metallurgy and electrically bonded by wire bonding or Tape Automated Bonding techniques. Electrical components are applied to the region of the second metallurgy and electrically bonded by flip-chip technique.

Solder bump transfer for microelectronics packaging and assembly

The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, or spaced therefrom by a thin layer of resistive material, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

Clustered field emission microtips adjacent stripe conductors

The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

Field emission microtip clusters adjacent stripe conductors

The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70; illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, or spaced therefrom by a thin layer of resistive material, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.

Three dimensional assembly of integrated circuit chips

A flexible polyimide film is used to support an array of precisely located contact bumps which are used to probe die on a wafer of semiconductor circuits, or an unmounted integrated circuit die, several integrated circuits, or hybrid devices. By utilizing a standard I/O contact pattern for the flexible film and fabricating the membrane assembly of interconnects on an aluminum substrate, it is possible to produce a more reliable probe card, while reducing the fabrication time and costs for the probe card. The polyimide film must be selected to have a CTE of 3 to 5, which is only about 1/5 to 1/7 as great as the CTE of the aluminum substrate on which the film is formed. This produces a critical degree of compressive stress in the polyimide film, and a resulting 'bow' of the film when the central area of the aluminum is etched away.

Method for fabrication of probe card for testing of semiconductor devices

Disclosed is a burn-in test socket which serves as a temporary package for integrated circuit die, multichip hybrid or a complete wafer without damaging the bonding pads or insulating passivation on the die during test and burn-in.

Non-destructive burn-in test socket for integrated circuit die

A method for making integrated circuits in which a polyimide/conductor multilevel film (17) in cast on a substrate (10), using available or existing semiconductor processing equipment. The polyimide film (17) is formed from readily available polyamic acid resins, and the conductor (16) can be sputtered aluminum formed to interconnection conductor patterns (16,16-) by standard photolithographic techniques. After fabrication of the multilayer film (17), the conductors (16,16') of the film (17) and the device circuit (30) are brought into aligned contact, and the device circuit (30) affixed to the film (17). The film (17) and the device circuit (30) are then removed from the substrate (10) for further processing, such as bonding the device and film to a mother board or leadframe, as desired.

Integrated circuit product having a polyimide film interconnection

A method for making integrated circuits in which a polyimide/conductor multilevel film is cast on a substrate, using available or existing semiconductor processing equipment. The polyimide film is formed from readily available polyamic acid resins, and the conductor can be sputtered aluminum formed to interconnection conductor patterns by standard photolithographic techniques. After fabrication of the multilayer film, the conductors of the film and the device circuit are brought into aligned contact, and the device circuit affixed to the film. The film and the device are then removed from the substrate for further processing, such as bonding the device and film to a mother board or leadframe, as desired.

Method for producing an integrated circuit product having a polyimide

A method for the fabrication of a cured polyamic acid film having apertures therein selectively etched to provide sidewalls sloped at a controlled angle. Such films are used in the fabrication of integrated circuits having two or more levels of metallization, to provide electrical insulation between metal levels. The apertures therein are required to have sloped sidewalls in order to enhance the yields of circuits having reliable contact between metal levels.

Process for etching sloped vias in polyimide insulators

A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are 'oversized' in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

Growing community of inventors

Richardson, TX, United States of America

Arthur M Wilson