Hughes Aircraft Company

Arthur L Morse

Mary J Hewitt

Steve D Gaalema

Ingrid M Keimel

Thomas Y Chuh

Niels A Thompson

A Sigma Rho A/D converter (10) includes a transconductance element (R) having an input node for receiving an input voltage signal V.sub.in and an output node providing an analog current I.sub.in ; a charge integrator (12) having an input coupled to the output node, the charge integrator having feedback provided by an integrating capacitor C and an output node providing an output signal V.sub.o ; and a clocked voltage comparator (14) having an input coupled to V.sub.o for comparing V.sub.o to a reference potential. An output of the comparator updates in response to an occurrence of a first clock signal CLK1. A current sink (16) is switchably coupled to the output node of the transconductance element as a function of the logic state of the output of the comparator. A sum and dump accumulator (18) has an input coupled to the output of the comparator and an output having N output bits, and operates to sum together individual ones of first logic states and outputs a sum value on the N output bits in response to an occurrence of a second clock signal CLK2. The frequency of CLK2 is equal to CLK1/N. A unique bit stream is output from the comparator (14) for each allowed input voltage such that complete information about the input voltage is embedded within, or encoded by, the bit stream output from the comparator.

Charge integrating-type analog to digital converter employing rapid

An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal. In still another embodiment the output stage 128 includes a second capacitor 132 of smaller capacitance onto which a charge of the first capacitor 130 proportional to the output of the amplifier stage is placed for subsequent sampling.

Integrating capactively coupled transimpedance amplifier

An analog-to-digital converter system for converting an input analog signal having a wide dynamic range to a digital output has a non-linear function generator for compressing the wide dynamic range input signal to a reduced dynamic range signal, an analog-to-digital converter of limited dynamic range for converting the reduced dynamic range signal to a digitally formatted signal, and a conversion memory for providing a digital value corresponding to the value of the wide range analog input. The digitally formatted signal addresses a word within the conversion memory, the word so addressed containing a digital value corresponding to the magnitude of the analog input signal. Each word of the conversion memory has a sufficient number of bits for expressing the desired dynamic range of the input signal. In one embodiment of the invention a digital counter and a digital to analog converter provides for calibrating the system, the output of the counter being stored in the conversion memory which, in this embodiment, is composed of RAM data storage elements.

Large dynamic range analog to digital converter

Integrating capacitively coupled transimpedance amplifier

A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26, which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.

Noise immune infrared readout circuitry and technique

A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26 which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.

Noise immune infrared readout circuitry

A method and circuit for reading out the detector signal current from an infrared focal plane array by converting the detector current into a precisely proportional charge packet which is injected into the channel of a charge-coupled device (CCD). In a preferred embodiment the circuit comprises a capacitive feedback transimpedance amplifier 30 (or similar infrared detector signal encoding circuit) coupled to a precision CCD charge-injection circuit 10 formed on a semiconducting substrate 12. A surface potential well 50 underneath a reservoir gate electrode 80 is filled with charge that is initially kept in place by a channel stop 14 and a potential barrier 62. When the detector signal is applied to signal gate electrode 60, the potential barrier 62 is lowered and a precisely proportional amount of charge fills a store potential well 48 underneath a store gate electorde 85. At an appropriate time the charge in the storage potential well 48 is transferred to CCD channel 90 by means of a clock pulse applied to a transfer gate electorde 100.

Low-noise charge-injection method and apparatus for IR CCD scanning

Noise reduction and dynamic range expansion in a CCD imager is achieved by combining a narrow FAT zero metering gate with a reference column subtraction and CCD charge bailing.

Growing community of inventors

Hawthorne, CA, United States of America

Arthur L Morse