Compaq Computer Technologies Group, L.p.

Arthur Klauser

Keith Farkas

Guard prediction apparatus for predicting guard outcomes for predicated instructions, each of which specifies a guard operator to be applied to a guard source to generate the guard outcome. The guard prediction apparatus includes a cache, availability logic, a selection circuit, a deduction circuit and write back circuitry. The cache stores previous predictions of guard outcomes for a set of guard sources and guard operators. The availability logic determines whether the cache includes a previous prediction that is relevant to a first guard source and a first guard operator and, if so, couples that previous prediction to the selection circuit. The selection circuit generates the final guard outcome prediction by selecting between the previous prediction, if available, and an initial prediction, if a previous prediction is not available. The deduction circuit deduces from the initial prediction of the guard outcome other consistent guard outcomes for a set of guard operators when applied to the guard source. The write back circuitry writes the initial prediction and the deduced guard outcomes into the cache for future use.

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Brookline, MA, United States of America

Arthur Klauser