Texas Instruments Corporation

Arthur John Redfern

Chenchi Luo

Timothy David Anderson

Kai Chirca

Fernando Alberto Mujica

Nirmal Chindhu Warke

Dan Wang

Patrick Satarzadeh

Asheesh Bhardwaj

Milind Anil Borkar

Kun Shi

Zhenhua Yu

Michael Oliver Polley

Donald Edward Steiss

Charles Sestok

Tarek Aziz Lahlou

Nadeem Ahmed

Guolong Su

Anand Ganesh Dabak

Mihir Narendra Mody

Marco Corsi

Alan Gatherer

Georgios Ginis

Venkatesh Srinivasan

Donald Phillip Shaver

Udayan Dasgupta

Krista S Jacobsen

William Franklin Leven

Yaser M Ibrahim

Victoria Wang

Asheesh Bhadwaj

Ming Ding

A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.

Computational primitives using a matrix multiplication accelerator

A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.

Matrix transfer accelerator system and method

A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.

Matrix compression accelerator system and method

Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA)

A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result. The RMM anticipates the use of 8, 16, and 32-bit operand reconfigurable matrix datum in conjunction with a typical external memory bus data width of 512 bits and an instruction control unit (ICU) implemented using a series of RMM configuration words (RCW) and streaming opcode functions (SOF).

Reconfigurable matrix multiplier system and method

A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.

Merge sort accelerator

An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.

Outer product multipler system and method

For protecting a speaker, an input signal is received, and an excursion of the speaker that would be caused by the input signal is predicted. In response to the predicted excursion exceeding a threshold, a targeted excursion of the speaker is determined by compressing the predicted excursion. The targeted excursion is translated into an output signal, which is output to the speaker.

Method and system for excursion protection of a speaker

A bandpass filter includes a plurality of parallel paths. Each path includes a first mixer, a low-pass filter, and a second mixer. The first mixer in each path receives the input signal and mixes the input signal with a periodic mixer sequence. The low-pass filter in each path is operable to filter an output of the associated first mixer. The second mixer in each path is coupled to receive an output of the associated low-pass filter and mixes said filter output with a periodic mixer sequence having a period that is divided into a plurality of time slots, wherein again the mixer value is constant during each time slot. A summer sums the outputs of the second mixers of each of the paths to generate an output of the bandpass filter.

Mixer sequence design for N-path filters

A bandpass filter includes a plurality of parallel paths, each receiving the input signal to the bandpass filter. Each path includes a first mixer, a low-pass filter, and a second mixer. The first mixer in each path is coupled to receive the input signal and mixes the input signal with a periodic mixer sequence having a period that is divided into a plurality of time slots. The mixer value is constant during each time slot. The low-pass filter in each path is operable to filter an output of the associated first mixer. The second mixer in each path is coupled to receive an output of the associated low-pass filter and mixes said filter output with a periodic mixer sequence having a period that is divided into a plurality of time slots, wherein again the mixer value is constant during each time slot. A summer sums the outputs of the second mixers of each of the paths to generate an output of the bandpass filter.

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Plano, TX, United States of America

Arthur John Redfern