Intel Corporation

Arthur Hunter, Jr

Joydeep Ray

Altug Koker

Abhishek R Appu

Prasoonkumar Surti

Vasanth Ranganathan

Subramaniam M Maiyuran

Scott R Janus

Lakshminarayanan Striramassarma

Elmoustapha Ould-Ahmed-Vall

Murali Ramadoss

Kamal Sinha

Mike MacPherson

Brent E Insko

Varghese George

Aravindh V Anantaraman

James A Valerio

Valentin Andrei

Vikranth Vemulapalli

Nicolas C Galoppo Von Borries

Balaji Vembu

Guei-Yuan Lueh

Ben J Ashbaugh

Sungye Kim

William B Sadler

Jonathan D Pearce

Yoav Harel

Zohar Bogin

Wei-Yu Chen

Ashutosh Garg

Eric J Hoekstra

Brent D Chartrand

Ankur N Shah

Aditya Navale

David M Puffer

Peter L Doyle

Jeffery S Boles

Pattabhiraman K

Kalyan Kumar Bhiravabhatla

Marian Alin Petre

Shailesh Shah

Mihir D Shah

Andrei Valentin

Chee Hak Teh

Selvakumar Panneer

Niranjan L Cooray

Vidhya Krishnan

Saurabh Tangri

Kritika Bala

Amandeep Singh

Kenneth Daxer

Abhinav Srivastava

Kalyan Bhairavabhatla

Rashmi Agarwal

Mohit Choradia

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Multi-render partitioning

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Sparse optimizations for a matrix accelerator architecture

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Multi-tile memory management

An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.

Tessellation redistribution for reducing latencies in processors

Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

Multi-tile graphics processor rendering

Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

Multi-tile architecture for graphics operations

Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Data prefetching for graphics data processing

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

Register spill/fill using shared local memory space

An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

Intelligent graphics dispatching mechanism

Growing community of inventors

Cameron Park, CA, United States of America

Arthur Hunter, Jr