Goodrich Corporation

Arthur Howard Waldie

Robert Ward James

Michael L White

Timothy John Canales

Kuo-Chuan Chang

A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.

Programmable throttle circuit for each control device of a processing system

A digital processing system comprises a central processing unit (CPU) operating in a virtual address domain for executing both operating system software and user software to perform various processing tasks; a direct memory access (DMA) controller; a memory management unit (MMU) programmed to translate virtual memory addresses to physical memory addresses; and a plurality of memory blocks for storing digital words in registers having physical addresses; wherein the DMA controller is governed by the CPU and is operable in the virtual address domain for controlling a transfer of digital words from a source block of memory to a destination block of memory through the MMU which translates the virtual source and destination memory addresses received from the DMA controller to corresponding source and destination physical addresses of the memory. Also disclosed is a method of operating the digital processing system.

Digital processing system including a DMA controller operating in the virtual address domain and a method for operating the same

A memory management unit (MMU) of a digital processing system operating in a virtual address domain and a physical address domain comprises a memory programmable to store translation mappings between virtual addresses and physical addresses of the processing system. The memory is also programmable to store control codes representative of EDAC protection corresponding to the translation mappings. A method of operating the memory management unit (MMU) comprises the steps of: programming a memory of the MMU with virtual to physical address translation mappings; and programming the memory of the MMU with control codes representative of EDAC protection corresponding to the translation mappings.

Memory management unit with programmable EDAC descriptors

A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. At least three data capturing circuits operate to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.

Fault tolerant storage cell

A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of the registers for generating an output signal of the logic cell; and a circuit coupled to each latching register for altering selectively the scan chain data signal input thereto. A scan chain test system for and method of testing at least one multiple voted logic cell of the aforementioned type are also disclosed.

Growing community of inventors

Albuquerque, NM, United States of America

Arthur Howard Waldie