International Telephone and Telegraph Corporation

Arthur Howard Magnus

James Monroe Clark

Stuart Barry Cohen

Each of first N flip-flop stages, where N is an integer greater than one, has steered thereto an appropriate one of N bits of the data to be transmitted by a transmit write counter and a first N stage decoder under control of a transmit write clock. A transmit read counter under control of a transmit read clock steers the stored bits to a transmit data bus by means of a first multiplexer and first logic circuitry under control of a transmit read counter and a transmit channel timing signal. Each of second N flip-flop stages has steered thereto an appropriate one of N bits of received data by a receive write counter and a second N stage decoder under control of a receive write clock. A receive read counter under control of a receive read clock steers the stored bits to a receive data bus by means of a second multiplexer and second logic circuitry under control of the receive read counter.

Transmit and receive digital data channel elastic store

An asynchronous digital time division multiplexer and demultiplexer combination at one communication terminal is disclosed that will multiplex first N asynchronous source data signals having a first mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the total of the bit rates of the source data and to demultiplex second N asynchronous source data signals having a second mixture of different bit rates from a received synchronous data stream having the predetermined fixed data format and the given bit rate. The combination includes an automatic channel assignment circuit to assign channels of the two data streams to the asynchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates by assigning the data signals to channels of the associated one of the two data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the two data streams. The channel assignment control circuit also includes a means to automatically indicate when the total of the mixture of bit rates has exceeded an allowable maximum.

Asynchronous multiplexer and demultiplexer combination

A transmit phase locked loop receives data to be transmitted having a bit rate equal to a first given one of a predetermined number of different bit rates. A diphase demodulator responds to the transmit phase locked loop and the data to be transmitted to provide output data for transmission. A receive write timing signal and a receive read timing signal is coupled to a receive phase locked loop to compare the phase relation of the two timing signals. A diphase modulator responds to received data having a bit rate equal to a second given one of the predetermined number of different bit rates and a clock signal provided by the receive phase locked loop to provide output data for utilization. The first given one of different bit rates and the second given one of different bit rates may have equal or different bit rates.

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Succasunna, NJ, United States of America

Arthur Howard Magnus