U.S. Philips Corporation

Arthur H Van Roermund

Petrus M Coppelmans

Eduard Ferdinand Stikvoort

Marcellinus J Pelgrom

Theodoor A Claasen

Peter J Naus

Albert J Stienstra

Petrus J Kamp

Antonius J Jochijms

Johan H Hendrickx

An impedance transformation circuit for transforming a two-pole electrical impedance (Z) includes a first controllable current source for producing a current (I.sub.1) flowing through the impedance during operation. An operational amplifier is coupled to the first current source for providing a control signal (V.sub.0) corresponding to the impedance current (I.sub.1). A second controllable current source is coupled to the operational amplifier for providing at an input terminal of the circuit a further current (I.sub.2) proportional to the impedance current (I.sub.1) as a function of the control signal (V.sub.0). As a result of using a first and second controllable current source and applying the control signal delivered by the operational amplifier to the control inputs of the two current sources, an impedance transformation is obtained which is dependent on similar parameter ratios. The circuit is suitable for use as an integrated semiconductor circuit.

Impedance transformation circuit with matched current sources

The invention relates to a semiconductor device including a charge transfer device having an output stage (8). The output stage (8) has a read-out zone (9), a feedback capacitor (11) and an amplifier (10). An inverting input (15) of the amplifier (10) is connected to the read-out zone (9) and an output (16) of the amplifier (10) is fed back via the feedback capacitor (11) to the inverting input (15). According to the invention, the capacitor (11) is a capacitor of the MOS type and means are provided by which during operation of the charge transfer device the surface potential of a surface region (13) in the capacitor (11) is solely determined by the potential of the read-out zone (9). Consequently, the capacitance of the feedback capacitor (11) is dependent upon the potential across it, as a result of which there is a linear relation between the charge supplied to the read-out zone (9) and the voltage variation across the capacitor (11 ). Thus, this voltage variation is an accurate measure of the supplied charge.

Charge transfer device having capacitive feedback

A switched capacitor network includes an input terminal (2) an output terminal (2), a series arrangement of a first and a second switching transistor, each having a control electrode (S.sub.1) for receiving a first (S.sub.1 ) and a second switching signal, respectively, and a capacitance between the junction point of the two switching transistors and a point of constant potential. The two switching transistors have a zone in common and the capacitance (S.sub.s) is exclusively constituted by the parasitic capacitance of the zone (17). This structure results in a switched capacitor network with an increased time constant.

Switched capacitor network

Arrangement for decoding a stereo multiplex signal, having a baseband stero signal (L+R), a stereo difference signal (L-R) which is amplitude-modulated on a suppressed sub-carrier, and a pilot signal having a frequency located between the frequency bands of the two signals, the arrangement having an input for the stereo multiplex signal and left and right stereo signal outputs, the input being coupled both, via a pilot selection circuit, to a phase-locked loop for regenerating the sub-carrier and to a multiplier circuit for multiplying at least the modulated stereo difference signal by the regenerated sub-carrier. In order to improve the stereo channel separation, the pilot selection circuit includes a bandpass filter of the switched capacitor type, a clock input of which is coupled to an output of an voltage-controlled oscillator incorporated in the loop. A mono-stereo control can be realized therein in a simple manner by varying the phase transfer of the switched capacitor bandpass filter at least at the pilot frequency in dependence upon a mono-stereo control signal.

Arrangement for decoding a stereo multiplex signal

A switched-capacitor multiplier circuit for multiplying an information signal x(t) by a bipolar carrier signal d(t) consisting of a distributed multiplier circuit with which the bipolar carrier signal is normally associated. To reduce offset voltages in the output signal caused by the operational amplifiers used and caused as a result of clock feed-through, it is not the bipolar carrier signal itself, but a full-wave rectified version thereof that is associated with the distributed multiplier circuit. The output signal of the multiplier circuit is applied to an auxiliary multiplier circuit multiplying it by +1 or -1 dependent on the instantaneous polarity of the bipolar carrier signal d(t). The offset voltage is thereby transposed to a frequency which is at least equal to the fundamental frequency of the carrier signal so that, if desired, it can be suppressed with the aid of a suitably chosen low-pass filter without the desired signal being affected thereby.

Switched-capacitor multiplier circuit

A time-discrete amplitude-continuous or a time-discrete amplitude-discrete signal is converted in to a 1-bit encoded signal by means of a quantizer, the quantization-error signal being fed back via a loop filter. The transfer function of the loop filter is given by H(Z)=1-(Z-b).sup.n /(Z-a).sup.n, where n.gtoreq.3, b.perspectiveto.1 and 0&lt;a&lt;b. In order to preclude, the input signal of the loop filter is limited by a limiter.

Encoding device

A first resistor (R.sub.1) and a first capacitor (C.sub.1) constitute a filter arrangement having a time constant which is not very accurate due to the inaccuracy of the resistor and the capacitor values in integrated circuits. The time constant is adjusted using a circuit comprising a reference resistor (R.sub.2) and a switched capacitor (C.sub.3). The value of the reference resistor (R.sub.2) and the equivalent resistance of the switched capacitor (C.sub.3) are compared by means of an integrator (C.sub.2, 2) from whose output (9) a control voltage is taken via a hold circuit (C.sub.4, C.sub.5). The control voltage is equal to the voltage at that point on the reference resistor where the resistance value is equal to that of the switched capacitor (C.sub.3). By means of comparators (21 to 30) and switches (S.sub.11 to S.sub.20) a percentage of the total resitance of the first resistor (R.sub.1) is short-circuited. This percentage is equal to the difference between the resistance of the reference resistor (R.sub.2) and the equivalent resistance of the switched capacitor (C.sub.3), expressed as a percentage of this equivalent resistance.

Integrated RC filter with resistor trimming

Multiplying circuit for multiplying a first signal x(t) by a periodic second signal y(t) and being particularly suitable for use as an amplitude demodulator in a stereo decoder or in a phase-locked loop. It comprises N signal channels 26(k) wherein k=0, 1, . . . n-1, each receiving the first signal x(t) and each producing a channel signal. Each signal channel is formed by, arranged in cascade, a switched-capacitor circuit 28(k;1), 28(k;2), 29(k), the circuit included in the signal channel being controlled by a train of control pulses g(k,i) which each have a finite duration and occur with a repetition period T.sub.o and at instants t.sub.o +k(T.sub.o /N)+iT.sub.o where i= . . . -2, -1, 0, 1, 2, 3, . . . , means 29(k), 31, 30 for multiplying the amplitude of the signal x(t) by a constant weighting factor W(k) which is equal to y(t.sub.o +k(T.sub.o /N), pulse-reshaping means 29(k), 30, 31 for converting a pulse applied thereto into a pulse having a predetermined duration. The channel signals thus obtained are added together in an adder device 30, 31 to form a sum signal. This sum signal is sampled in a sampling arrangement 34(1), 34(2), 35 at instants comprised within the interval between the end of a control pulse g(k,i) and the beginning of the subsequent control pulse g(k+1,i).

Multiplying circuit comprising switched-capacitor circuits

A phase-locked loop has a phase detector and a clock pulse oscillator. The phase detector multiplies a received reference signal by a comparison signal. It is constituted by a plurality of signal channels 207 each receiving the reference signal and having a cascade arrangement of a switching circuit 208 and a weighting network 209. The switching circuit is controlled by one or more sequences of main control pulses supplied by a pulse distributor circuit receiving clock pulses. Each signal channel has a constant weighting factor. For the k.sup.th signal channel the weighting factor is equal to the signal sample n(t.sub.o +kT.sub.s) of a fundamental signal n(t) which has a fundamental frequency f.sub.o. T.sub.s is the reciprocal of the clock pulse frequency f.sub.s. For each sequence of main control pulses controlling the switching circuit in the k.sup.th signal channel, this signal channel produces a main signal z(k, t). The main signals supplied by all the signal channels are added together. To allow locking of the loop on frequencies which are an integral multiple p of the fundamental frequency, the clock pulse oscillator has a frequency f.sub.s which is an integral multiple N of the fundamental frequency. In addition, the pulse distributor circuit has an input for setting the parameter p and at least N distributor outputs to which the several clock pulses are applied. More specifically, the clock pulse having number n is applied to the distributor output having number np modulo N. The sequence of pulses thus occurring at these distributor outputs constitutes the sequence of main control pulses.

Phase-locked loop with switchable phase detector

A clock-controlled filtering arrangement for suppressing a number of interference frequencies related to a clock frequency, which comprises a time-discrete comb filter included in a negative feedback loop for a selective negative feedback of the said interference frequencies, which time-discrete comb filter is connected to an output of a clock generator for controlling the frequency location of the pass ranges of the comb filter. In order to avoid on the one hand the introduction of quantizing noise and the use of additional circuits, such as A/D and D/A converters, and on the other hand the occurrence of error cumulation while maintaining an adequate interference suppression, the time-discrete comb filter is of the switched capacitor N-path filter type.

Clock-controlled filtering arrangement

Band-rejection filter of the switched capacitor type in which at least one unwanted frequency component present in an information signal must be suppressed. To that end this filter comprises and adding circuit 4 to which the information signal is applied via a switching device 3 and a feedback signal via a switching device 5. Both switching devices are controlled by a first control signal consisting of a sequence of control signal periods of a duration T.sub.s which are each divided into a tracking phase and into an interrupt phase. During the tracking phase the signal can pass uninterruptedly through the switching device, while during the interrupt phase signals are not allowed to pass. The output of adding circuit 4 is coupled inter alia via a switching device 8 to the input of a bandpass filter 9 whose passband at least coincides with the unwanted frequency component. The switching device 8 is controlled by a second control signal which is also formed by a sequence of control signal periods of a duration T.sub.s and which are each divided into a tracking and an interrupt phase. In order to realize an adequate suppression of the unwanted frequency component the instants at which the tracking phases in the first control signal and the tracking phases in the second control signal end are mutually phase-shifted over a fixed distance.

Band-rejection filter of the switched capacitor type

Multiplier circuit for multiplying an information signal x(t) by a periodic signal y(t) having frequency f.sub.o, more specifically for amplitude modulation purposes in a stereo decoder. The multiplier circuit comprises N switching circuits 21(k) wherein k=0, 1, . . . N-1 which are each connected to a clock pulse generator 221, 222 by means of a control channel 25(k) and are each connected to an input of an adder device 28 by means of a signal channel 26(k). In addition, each switching circuit 21(k) receives the information signal x(t). A series of clock pulses g(k;t) is applied to each control channel in such a manner that for the control channel having number k these clock pulses occur at the instants t.sub.o +k(T.sub.o /N)+iT.sub.o wherein t.sub.o represents a constant T.sub.o =1/f.sub.o and i=. . . , -2, -1, 0, 1, 2, . . . Each signal channel 26(k) comprises a weighting network 27(k) having a constant weighting factor W(k) defined by the relation W(k)=y(t.sub.o +k(T.sub.o /N)). Each control channel 25(k) (or each signal channel 26(k)) incorporates a pulse reshaping circuit 24(k), which converts a pulse applied thereto into a pulse having a width equal to .tau.=T.sub.o /M wherein M represents an integer, for example M=N-1.

Multiplier circuit for multiplying an information signal by a periodic

A dynamic amplifier circuit, specifically for switched-capacitor filters, having a current source which supplies an exponentially-decreasing bias current. In addition, a current source is included for supplying an additional bias current in order to define the minimum bias current in the amplifier circuit.

Dynamic amplifier circuit

Charge transfer devices exhibit transfer inefficiencies, so that a part of a transferred charge packet is left and lags the original charge packet. This results in 'smearing' of the original charge packet, thereby adversely affecting the unit-function response and the frequency response of the charge transfer device. The invention provides a solution to this problem, utilizing a compensation charge derived from the original charge packet, which at a suitable instant is applied to a point where the residual charge is cancelled via a feedback loop.

Compensation of 1st order transfer inefficiency effect in a C.T.D.

A method and device in which both positive and negative signal charges can be transferred from a first capacitance to a first point via a transistor circuit which exhibits a threshold level. For this purpose the first capacitance contains a reference charge with a positive or a negative polarity. First, the voltage on the first point is switched so that the first capcitance is charged from said first point and subsequently so that the first capcitance discharges towards the first point to its reference charge, which corresponds to said threshold level, in such a way that the net charge transfer from the first capacitance to the first point is equal to the positive or negative signal charge and the charge on the first capacitance is restored to a reference level.

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Eindhoven, Netherlands

Arthur H Van Roermund