Itt Corporation

Itt Gallium Arsenide Technology Center, a Division of Itt Corporation

Itt Gallium Arsenide Technology Center

Itt a Division of Itt Corporation Gallium Arsenide Technology Center

Arthur E Geissberger

Robert A Sadler

Matthew L Balzan

Gregory E Menk

Edward L Griffin

Paulette Luper

Philippe R Claytor

A new GaAs FET structure is provided by a process which provides a GaAs channel between AlGaAs layers and wherein the GaAs channel has a higher active carrier concentration than either adjacent AlGaAs layer.

Heterojunction confined channel FET

A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact 'windows' through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.

Self-aligned gate realignment employing planarizing overetch

A high speed GaAs FET is provided by forming a sandwiched GaAs channel between AlGaAs layers and employing an Si implant to provide channel doping for the GaAs channel. The poor activation efficiency of Si in AlGaAs relative to its activation efficiency in GaAs provides a channel having a higher active dopant concentration than exists in the adjacent sandwiching layers. This tends to enhance conductivity in the channel relative to the sandwiching layers.

GaAs FET manufacturing process employing channel confining layers

A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET's have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtained from a self-aligned FET.

Method of making self-aligned field-effect transistor

A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer, whereon is formed a first AlGaAs layer having a first mole fraction of Al and a second AlGaAs layer having a second mole fraction of Al higher than the first mole fraction. As intrinsic GaAs channel layer is formed on the second AlGaAs layer.

Method of making sagfets on buffer layers

A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer. A layer of GaAlAs is then provided such that the Ai content and no doping followed by an intrinsic GaAs layer. The intrinsic GaAs layer is the active layer which serves as a channel.

Sagfet with buffer layers

A process for manufacturing GaAs FET's having refractory metal gates provides for reducing the size of the gate relative to a mask by an etch sequence which results in precisely controlled and repeatable self-limited undercutting of the mask. A reactive ion etch of the refractory metal in a CF.sub.4 O.sub.2 plasma containing an inert gas provides the self-limiting undercut at a pressure in the range of 175-250 mTorr when the power is less than 0.15 W/cm.sup.2. Preceeding the undercut, an anisotropic RIE in a CF.sub.4 plasma can be employed to clear unmasked areas of the refractory metal and an initial sputter cleaning in argon improves the quality of the initial etch.

Self-aligned refractory gate process with self-limiting undercut of an

The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

Self-aligned gate FET process using undercut etch mask

A process for manufacturing gallium arsenide microwave circuits makes use of a nonphotosensitive acid resist as an adhesive for holding the 'front side' of a gallium arsenide wafer onto a substrate while operations such as etching 'via holes' into the wafer are being performed on the 'back side' of the wafer. The process comprises front side processing, spinning the nonphotosensitive acid resist onto the frontside of the GaAs wafer, baking the protective acid resist coating onto the wafer, spinning the acid resist onto a substrate, joining the wafer to the substrate, thinning the wafer, and performing backside processing.

Process for manufacturing gallium arsenide monolithic microwave

A method of making a field-effect transistor includes performing a first ion implant in at least one region of a gallium arsenide substrate and forming a metallization layer of titanium-tungsten nitride on the implanted substrate. A metallic gold masking layer is deposited on the metallization layer over the implanted region and that portion of the metallization layer which is unmasked is removed. A self-aligned source of implantation ions is beamed into the first implanted region in those areas not covered by the masking layer. The substrate is then annealed to activate the implanted region with the gold masking layer remaining to greatly reduce the resistance of the gate electrode of said field-effect transistor.

Growing community of inventors

Roanoke, VA, United States of America

Arthur E Geissberger