International Business Machines Corporation

Arthur E Fleek

William O Camp, Jr

Michael J Bracco

Richard D Bolcavage

Gary M Warchocki

Armand J Ferraro

Samuel C-c Tseng

Richard Orville LaMaire

Glenn W Davis

Mitchell P Marcus

Ralph Yeager

Richard O Lamaire

A phase shift modulator at the transmitter has a control input connected to a binary signal source. A high frequency carrier signal is applied to a carrier signal input of the modulator. The modulated carrier signal is transmitted to a receiver where it is mixed with a local oscillator frequency. At the receiver, a modulated signal is amplified by a limit amplifier to form the received signal into square wave pulses of a uniform height. The demodulator detects when the spacing between the edges of the square wave signal change in response to the phase shift modulation at the transmitter. When the spacing between the edges of the square wave IF signal is detected to be shorter than the normal spacing for a steady IF signal with no modulation, this signifies a first binary value. A longer than normal spacing between the edges of the square wave IF signal signifies a second binary value. Frequency drift compensation circuits are disclosed to overcome frequency variations in the carrier and the local oscillator.

Phase demodulation method and apparatus for a wireless LAN, by counting

An apparatus and a method for detecting a carrier signal of a phase shift keyed modulated signal. A first counter circuit generates a plurality of counts, with each count being a number of cycles of a reference frequency signal occurring between two consecutive rising edges of an intermediate frequency signal. A comparison circuit compares a first count of reference frequency cycles to a second count of reference frequency cycles when a difference between an initial count of reference frequency cycles and a first predetermined number is less than a second predetermined number. The first predetermined number represents a time period of one cycle of the nominal center frequency, and the first count and the second count respectively represent time periods of first and second cycles of a pair of consecutive cycles of the intermediate frequency signal. The comparison circuit generates a difference signal when a difference between the first count and the second count is less than a third predetermined number. A second counter circuit counts cycles of the intermediate frequency signal and generates a carrier detect signal when a count of the intermediate frequency signal cycles equals a fourth predetermined number.

Digital delta mode carrier sense for a wireless LAN

The oscillator at the sending node of a wireless digital network, generates a carrier signal, starting at a first instant. A modulator coupled to the oscillator performs phase shift modulating of the carrier signal with an input signal. A spoiler signal generator is coupled to the modulator, for providing a spoiler signal as the input signal, starting at the first instant and continuing for a first duration which is longer than a period needed for the oscillator to achieve stable characteristics. A transmitter is coupled to the modulator at the sending node, for transmitting a wireless radio signal representation of the carrier signal phase shift modulated with the spoiler signal to a receiver at a receiving node. The spoiler signal in the modulated carrier signal interrupts the periodic characteristic of the pulses, and thereby prevents the carrier sensor from detecting the carrier signal. Further, the spoiler signal ceases to modulate the carrier signal after the first duration when the oscillator has achieved stable characteristics, thereby enabling the carrier sensor to detect the carrier signal.

Method and apparatus for digital carrier detection in a wireless lan

A carrier sensing circuit coupled to a receiving amplifier, measures the frequency of a phase shift modulated carrier signal by counting a predetermined number of the pulses for a measured interval whose duration is determined by counting a first clock count value. A demodulator coupled to the amplifier, detects when the spacing between the edges of the square wave pulses changes in response to the phase shift modulation. The demodulator measures first intervals between consecutive rising edges of the received signal, by counting clock pulses for a second selected interval whose duration is determined by a second selected count value. The demodulator further measures second intervals between consecutive falling edges of the received signal by counting clock pulses for a third selected interval whose duration is determined by a third selected count value. A compensating circuit coupled to the carrier sensing circuit and to the demodulator, compensates for frequency drift in the carrier signal or in the local oscillator by adjusting the second selected count value and the third selected count value, using the first clock count value.

Method and apparatus for digital frequency compensation of carrier drift

A method for use in a single cell of a wireless communication system of the type having a leader station that coordinates communication among a plurality of remote stations that are in the cell. The method applies to systems that use slow frequency-hopping radios and a Carrier Sense Multiple Access (CSMA) type protocol. In this context, the method allows a remote station to initially acquire the frequency-hopping pattern and time base of the leader station and to maintain frequency synchronization in the face of control information loss due to radio transmission effects (e.g., interference, noise or multipath fading). In the acquisition phase, the remote station actively generates probe messages that are sent to the leader station so as to rapidly achieve frequency synchronization with the leader station.

Robust frequency management and acquisition in a wireless local area

A variable speed printing (VSP) adaptor for a dot matrix printer which includes a monitoring means having a plurality of devices each capable of assuming one of two states. The monitoring means monitors the state of the pattern data to be printed, and, in the preferred embodiment, the monitoring means comprises a counter which is preset with a number equal to the number of column scans with a dot print line. The pattern data to be printed is scanned in a forward direction, i.e., in the normal printing direction starting at the first print position and the count in the counter is decremented one count for each column data scanned. During the time interval between when this data is latched and the actual hammer actuation, the pattern data is scanned in the backward direction starting at the last print position. Each time the column data for a backward scan is zero, i.e., no dot to be printed, prior to sensing a non-zero column, the count in the counter is decremented one count. The printing operation continues in the interleaved forward/backward scans until the count in the counter reaches a reference level such as zero. Upon sensing this reference level in the counter, a control signal is generated which indicates that the printing of the dot row is complete and initiates movement of the paper to the next dot row position. In an alternate embodiment, the monitoring means comprises a random access storage device.

Variable speed printing for dot matrix printers

A printer control system for a belt printer has an arrangement for checking print hammer operating circuits by comparing a real time actual parity of the circuits with a precalculated expected parity. Prior to printing, a microprocessor calculates expected parity bytes for each subscan for storage in a storage device along with the print position fire data used for selecting the operating circuits to be activated in the related subscans. An actual parity byte is generated on a real time basis by ODD/EVEN parity circuits associated with groups of operating circuits for comparison with a composite parity byte generated each subscan by the microprocessor. The composite parity byte is generated by combining the expected parity bytes from the storage device for several successive subscans. The composite parity byte is updated each subscan by a process of subtracting the initial expected parity byte and adding a new subscan expected parity byte. Comparison is made when all the activating circuits are in stable condition.

Printer system having parity checking of print hammers using software

A control system for the carriage drive of a line printer includes a microprocessor which controls a carriage drive stepper motor through programmable timers and interface adapter along with other non-print units of a printer mechanism. A control counter in the carriage drive responsive to feedback pulses from the stepper motor coacts with the timers to control various operation of the stepper motor during line feeding of a print medium and is used by the microprocessor for preventing loss of control of the carriage drive due to interrupts from other devices.

Printer system having microprocessor control

A printer system comprising a belt printer mechanism controlled by a stored program digital microprocessor to print lines of data on a print medium. Selective operation of a linear array of print hammers, paper feeding, data conversion and arranging in scan/subscan order are performed by the microprocessor. The fire data for operating hammers is precalculated and arranged in scan/subscan order during the print medium feeding interval with printing occurring immediately at the first print scan after print medium motion in which one or more desired characters become aligned with print hammers. An indirect addressing technique which eliminates sorting is used to arrange the print position fire data in scan/subscan order.

Line printer system and method of operation with microprocessor control

A belt printer control system for attachment to a host system has a first microprocessor connected by a dedicated bus to the host system and control elements operable to perform carriage control, belt drive, and ribbon drive operations of the printer mechanism. A second microprocessor is connected by a dedicated bus structure to controls for operating the print hammers. A common RAM is accessed by the two microprocessors through a common bus structure. The first microprocessor passes control and print information to the RAM for use by the second microprocessor in building print algorithm tables in the RAM for use by the second microprocessor to operate the print hammers. Communication between the microprocessors is done through control information stored by the microprocessors in the common RAM. Storing printing information and building of tables and controlling printing and nonprinting operations of the print mechanism are done concurrently.

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Cary, NC, United States of America

Arthur E Fleek