International Business Machines Corporation

Arthur Davidson

Sadeg Mustafa Faris

Paul Andrew Moskowitz

William Joseph Gallagher

George A Sai-Halasz

Thomas K Worthington

Timothy Rea Dinger

Cheng-Chung J Chi

Dennis James Herrell

Chang-Chyi Tsuei

Improved conductors and superconducting magnets are described utilizing superconducting materials exhibiting critical field anisotropy. This anisotropy is one in which the ability of the superconductor to stay in a superconducting state depends on the orientation of a magnetic field applied to the superconductor with respect to the direction of current flow in the superconductor. This anisotropy is utilized in the design of conductors and magnet windings comprising the superconductive material and specifically is directed to magnet windings in which the direction of high critical current through the superconductor is parallel to the magnetic field produced by current in these windings in order to obtain high critical fields. Particularly favorable examples of a superconducting material are the so-called high T superconductors in which the primary supercurrent flow is confined to 2 dimensional Cu&mdash;O planes. By arranging the superconductive windings so that the Cu&mdash;O planes are substantially parallel to the magnetic field produced by current in these windings, the windings will be able to withstand high fields without being driven normal. This maximizes the magnetic field amplitudes that can be produced by the magnet.

High current conductors and high field magnets using anisotropic superconductors

This interface permits the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line interconnecting a first chip station, where the cryogenic chip is mounted, and a second chip station, where the semiconductor chip to be tested is temporarily mounted. The pass-through plug has a cemented long half-cylindrical portion and short half-cylindrical portion. The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall. The first chip station, with the cryogenic chip attached, extends into the liquid helium reservoir. The second chip station is in the room temperature environment required for semiconductor operation. Proper semiconductor operating temperature is achieved by a heater wire and control thermocouple in the vicinity of each other and the second chip mounting station. Thermal isolation is maintained by vacuum and seals. Connections for power and control, for test result signals, for temperature control and heating, and for vacuum complete the test apparatus.

Room temperature cryogenic test interface

A superconducting circuit including at least two DC SQUID stages integrated on the same superconducting chip and coupled by a circuit providing efficient transfer of current from the first SQUID stage to the second SQUID stage with large bandwidth. Each SQUID stage is comprised of a superconducting loop having at least two Josephson devices therein, there being shunt resistors across the Josephson devices to render them nonhysteretic. The coupling means between stages is directly connected to the shunt resistors of the first stage and includes a transmission line and an impedance circuit for matching the impedance of the transmission line, where the impedance circuit provides a real impedance over a large frequency range up to approximately the frequency of Josephson oscillation of the Josephson devices in DC SQUID. Feedback from the second SQUID stage to the first SQUID stage improves the input dynamic range and linearity of the circuit.

On-chip SQUID cascade

Josephson devices are distributed in series in a transmission line structure in which electromagnetic waves are used to synchronize the dynamics of the Josephson devices in order to achieve coherence between the devices. Electromagnetic waves, such as oscillatory traveling waves, standing waves, and solitary waves along the transmission line couple the Josephson devices in a manner such that coherence is achieved for the entire array. The Josephson devices can be tunnel junctions, point contacts, micro bridges, and weak links, and more generally include any such superconductive device which obeys the Josephson equations of voltage and current. The transmission line is any line which controllably supports electromagnetic waves, and can include strip lines located over a ground plane, coaxial lines, etc. A DC bias is supplied to the transmission line, and the ends are terminated in accordance with the type of wave to be propagated along the line. Each Josephson device couples to the electromagnetic wave along the transmission line where many Josephson devices can be in series. Typically, the Josephson devices are spaced closer than the wavelength of the electromagnetic wave, although this is not a necessity. The coherent array can be used for wave generation and detection, amplification, and as a voltage standard.

Distributed array of Josephson devices with coherence

A Josephson Self Gating And circuit which is powered by pulsed or clipped alternating current and provides true and complement outputs in response to true and complement inputs is disclosed. Inputs applied during the duration of the applied pulsed power or clipped alternating current are delivered to outputs which are maintained in that state in spite of a change of input within the given pulse duration. In one embodiment, the presence of an output signal interrupts a current path which, in turn, disables a pair of AND gates. These gates, even though the input to them changes, can provide no other output until the applied power falls to zero resetting the pair of AND gates which are latching in character. In another embodiment, current paths of one AND gate are cross-coupled with a current path of another AND gate. The interruption of current in a serially disposed Josephson device in one or the other of the current paths disables one or the other of the pair of AND gates preventing a change in outputs until the next cycle of applied pulsed or alternating current power. A latch circuit incorporating a pair of AND gates, a flip-flop and a Self Gating And circuit is also disclosed. The latch permits an input different from a previously applied input to the flip-flop to change the state of the flip-flop without changing the output of the Self Gating And during the application of a cycle of pulsed or alternating current power. The changed input to the flip-flop appears at the output of the Self Gating And circuit during the next cycle of applied pulsed or alternating current power.

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Yorktown Heights, NY, United States of America

Arthur Davidson