International Business Machines Corporation

Arthur D Tuminaro

Yuen H Chan

Antonio R Pelella

Ryan T Freese

Jatinder K Wadhwa

Uma Srinivasan

Rajiv V Joshi

Otto M Wagner

Philip T Wu

John R Rawlins

Timothy J Charest

William R Dachtera

Richard Edward Serton

Leonard C Ritchie

A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

Single clock dynamic compare circuit

A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a 'local bit select' circuit.

Global bit select circuit interface with dual read and write bit line pairs

Global bit select circuit with dual read and write bit line pairs

A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Global bit line restore timing scheme and circuit

A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

A domino SRAM is provided with active pull-up PFET devices that overwhelm 'slow to write but very fast to read' cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional 'bit select' clamp to actively control the &#x201c;local select&#x201d; through &#x201c;wired-or&#x201d; PFET pull-up transistors. Separate read and write global &#x201c;bit line&#x201d; pairs allow the read and write performance to be optimized independently.

Local bit select with suppression of fast read before write

Bit and write decode/drivers, a random access memory (RAM) including the decode/drivers and an IC with a static RAM (SRAM) including the decode/drivers. The decode/drivers are clocked by a local clock and each produce access pulses wider than corresponding clock pulses. The bit decode/driver produces bit select pulses that are wider than a word select pulse and the write decode/driver produces write pulses that are wider than the bit select pulses for stable self timed RAM write accesses.

Self timed bit and read/write pulse stretchers

A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Programmable sense amplifier timing generator

A memory sense amplifier includes a latch formed for interconnected CMOS gates with an input gate connected to one node of the latch and a reference gate connected to the other node of the latch the reference gate has an input connected to a source of reference voltage and the reference gate and input gate are activated in response to common enable signal. When the input signal, e.g., a data signal from a memory, has a signal value lower than the reference signal value when the two gates are enabled, the reference gate will discharge the node to which it is connected more rapidly than the input gate will discharge the other node. Due to the internal cross connections of the latch, the latch will rapidly change state so as to further discharge the node to which the reference is connected and further charge the other node. In this manner, a rapidly change of state of the latch is accomplished and a binary value output is generated at the latch thereby avoiding the delay which is normally encountered due to the time required for the input signal to achieve a complete change of state.

CMOS sense amplifier

A latch and driver circuit is disclosed for use in reading out data from a random access memory cell. The invention, which may be implemented in BICMOS technology, accomplishes high-speed asynchronous latching, level translation and output driving operations. The invention includes a latch and at least one output driver coupled in parallel to a latch driver.

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LaGrangeville, NY, United States of America

Arthur D Tuminaro