International Business Machines Corporation

Arthur C Winslow

Anthony K Stamper

Jeffrey P Gambino

Thomas L McDevitt

William J Cote

Xiaomeng Chen

William R Hill

Robert Zwonik

Kenneth E McAvey, Jr

Edward W Conrad

Timothy E Neary

Paul William Pastel

Dinh Dang

Paul D Sonntag

William John Adair

Kenneth F McAvey, Jr

Michael E Bailey

James J Colelli

James George Michael

Erik A Puttlitz

Sylvia R Tousley

Timothy J Toth

An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Method of fabricating copper damascene and dual damascene interconnect wiring

Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.

Method for reducing amine based contaminants

A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.

Semiconductor structure having reduced amine-based contaminants

A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper diffusion barrier layer; a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; a first capping layer on the top surface of the wire and the top surface of the dielectric layer; and a second capping layer on a top surface of the first capping layer.

Copper damascene and dual damascene interconnect wiring

Photolithography tools have alignment systems for aligning a level to be printed with a level already on the wafer. Commonly a photolithography tool has several alignment systems Also, wafers may have several alignment marks, and the various alignment systems may be capable of reading several of the alignment marks. The present invention provides a method of selecting the alignment system-alignment mark combination that gives the most accurate alignment to a previous level. The inventors found that residual errors provide a metric by which to evaluate alignment system-alignment mark combinations. The combination with the least residual error is selected. Alternatively data for actual overlay measurements is compared with alignment data for each alignment system-alignment mark combination, and the combination that has the best correlation to the overlay data is selected.

Dynamic alignment scheme for a photolithography system

Mask with attenuating phase-shift and opaque regions

In a plasma or RIE etching tool using a uniquely designed annulus around a wafer supporting pedestal, it has been found that the introduction of one or more gases in the region immediately adjacent the annulus controls the amount of etching of features in that region in the surface of the wafer mounted on the pedestal. By so controlling the amount of gas in this region, the slope of the walls of the etched features can be also controlled.

Symmetrical etching ring with gas control

Growing community of inventors

Essex Junction, VT, United States of America

Arthur C Winslow