Microsoft Technology Licensing, LLC

Intergraph Corporation

Intergraph Hardware Technologies Company

Arthur C McKinney

Vahid Samiee

Charles H McCarver, Jr

Jeff S Ford

Craig Jordan

A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to main memory, where each processor has an internal cache which is externally unreadable outside the processor. The method includes requesting data associated with a memory location in main memory and determining if an external cache coupled to an application specific integrated circuit associated with a second processor contains a reference to the requested data. A snoop cycle is performed on the second processor if the external cache has a reference to the requested data, whereupon a determination is made as to whether the requested data has been modified.

Multi-processor data coherency

A method and apparatus for packing and unpacking pixels using a shift-down register and a shift-up register. In general, the shift-down register and shift-up register have the same bit storage capacity. In addition, the shift-down register and the shift-up register have a bit storage capacity larger in size than the bit storage capacity of the memory device from which the pixels are unpacked, or to which the pixels are packed.

System and method for packing and unpacking video data

A high-availability parallel processing server has multiple processors that are grouped into processor clusters and a plurality of memory segments. Each cluster may have up to four processors, and there may be up to five clusters of processors. Each of the processor clusters has dedicated memory buses for communicating with each of the memory segments. The server may be designed to maintain coherent interaction between all processor clusters and the memory segments.

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Madison, AL, United States of America

Arthur C McKinney