Bell Telephone Laboratories

Arthur C Adams

Hyman J Levinstein

Thomas Azwell

Cesar D Capio

David N Wang

Loren Neil Pfeiffer

David E Aspnes

Kenneth William West

Ashok K Sinha

Brian G Bagley

Shyam P Murarka

Louis R Thibault

Frank B Alexander, Jr

Chloe Ciotti

The present invention provides a new and distinct variety of hemp designated as '3 Crop', wherein '3 Crop' comprises improved resilience to high salinity soil.

Hemp plant named '3 Crop'

The present invention provides a new and distinct variety of hemp designated as 'NaCl', which has improved resilience to high salinity soil and drought conditions, as well as tolerance to small rootzone conditions.

Hemp plant named 'NaCl'

The present invention provides a new and distinct variety of hemp designated as 'C2B', wherein 'C2B' comprises a cannabidiol:cannabichromene:tetryhydrocannabinol ratio of 25:9:1 which is 4-8 times greater than the average amount of cannabichromene found in othervarieties.

Hemp plant named 'C2B'

Disclosed are methods that result in substantial improvement of silicon-on-insulator (SOI) device manufacture. We have discovered that carbon can be advantageously used as a wetting agent in the melting-recrystallization (MR) method of producing SOI wafers. We have also found that contacting the wafer (typically subsequent to the formation thereon of a poly-Si layer on a SiO.sub.2 layer but prior to the completion of formation of a SiO.sub.2 cap layer on the poly-Si layer) with an atmosphere that comprises a wetting agent-containing molecular species (e.g., CH.sub.4, NH.sub.3), with the wafer at an appropriate elevated (e.g., 500.degree.-900.degree. C.) temperature, can reliably result in recrystallized Si films of high quality. Furthermore, we have discovered the existence of a previously unknown parameter regime (low thermal gradient across the resolidification front, typically no more than about 4.degree. C./mm) for the MR process that can result in a highly perfect (.chi.min of 3%, subboundary spacing of about 50 .mu.m, misalignment across subboundaries of the order of 0.1.degree.) resolidified Si layer. Devices can be fabricated directly in this layer, or the layer can be used as seed substrate for the growth of a 'thick' epitaxial Si layer of the type useful for the fabrication of high voltage semiconductor devices.

Method of producing SOI devices

Layers of controllably dopable amorphous silicon and germanium can be produced by means of low pressure chemical vapor deposition, at a reaction temperature between about 450.degree. C. and about 630.degree. C., for Si, and between about 350.degree. C. and about 400.degree. C. for Ge, in an atmosphere comprising a Si-yielding or Ge-yielding precursor such as SiH.sub.4 or GeI.sub.4, at a pressure between about 0.05 Torr and about 0.7 Torr, preferably between about 0.2 and 0.4 Torr. For undoped Si and P-doped Si, the preferred temperature range is from about 550.degree. C. to about 630.degree. C., for B-doped Si, it is from about 480.degree. C. to about 540.degree. C. The material produced has a density in excess of 0.9 of the corresponding crystalline density, and contains less than 1 atomic percent of hydrogen. An advantageous doping method is addition of dopant-forming precursor, e.g., PH.sub.3 or B.sub.2 H.sub.6, to the atmosphere. The material produced can be transformed into high quality crystalline material, and has many device applications in amorphous form, e.g., in solar cells, vidicon tubes, photocopying, and in integrated circuits, either as a conductor or nonconductor. The layers produced show conformal step coverage.

Method for producing devices comprising high density amorphous silicon

The efficient production of sequential layers of silicon dioxide and polycrystalline silicon is possible using a specific set of reaction steps. This set of reaction steps includes the oxidation of silicon at low oxygen pressure and at temperatures of the magnitude of 900 degrees C., followed by the deposition of polycrystalline silicon at substantially the same temperature utilizing a dichloride silane chemical vapor deposition (CVD) process.

Method for producing silicon dioxide/polycrystalline silicon interfaces

In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.

Reducing charging effects in charged-particle-beam lithography

A method of depositing doped silicon dioxide layers in the fabrication of semiconductor devices has been found. This method entails the reaction of a mixture of silane, nitrous oxide and a source of a dopant, e.g., phosphine or diborane. The reaction is performed at relatively high temperature, typically between 800 and 900 degrees C., and excellent step coverage is obtained. Further, the pinhole problems previously associated with high temperature techniques are avoided. Lower dopant concentrations, e.g., below 6%, are also practical.

Deposition of doped silicon oxide films

The discovery that boron nitride and boron carbide films can be made in tension allows nondistorting radiation windows or masks to be realized. Both low and high pressure techniques for making the tensile films lead to related mask structures utilizing such films. The resulting structures are sufficiently distortion free to be useful for x-ray lithography.

Radiation mask structure

Disclosed is a method and structure for protecting circuit components from the ambient and in particular for protecting the contact metal from the adverse effects of moisture. A first layer of amorphous silicon is deposited over the circuit including the metal contacts. A second layer which may be silicon nitride or silicon dioxide is then deposited over the amorphous silicon. The amorphous silicon layer reduces cracking in the second layer and prevents cracks in the second layer from propagating to the circuit components.

Growing community of inventors

Berkeley Heights, NJ, United States of America

Arthur C Adams