Wang Laboratories, Inc.

Arthur B Barrow

Kin L Cheung

Jeffrey W Einarson

Horace H Tsiang

Shams A Khan

Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register. Also disclosed is a method of prefetching in which the first instruction syllable is prefetched into the first instruction syllable register and each of the other syllables is prefetched in turn to the second instruction syllable register and a method of executing the EXECUTE instruction in which the syllables of the EXECUTE instruction are prefetched directly from memory using the instruction address and the syllables of the subject instruction are fetched into the data register and from there into the instruction syllable registers.

Instruction prefetcher

A multitasking data processing machine supports virtual memory comprising a plurality of segments, and has physical memory comprising relatively fast main memory and relatively slow secondary memory. A constantly varying subset of secondary memory paged contents is copied in main memory page frames. When a memory access is required during operation of the machine, a virtual address is generated, which must be translated into a physical address, in order to address main memory. The data processing machine provides an indexed local random access memory (T/RAM) for storing previously translated addresses. The T/RAM has a capacity of one entry for each page of supported virtual memory. Before a translation is performed, the T/RAM is indexed by the virtual address; in case of a T/RAM fault, translation is performed and the translated physical address is loaded to the indexed location before restarting the memory operation. A subsequent reference to the same virtual address indexes the previously translated physical address, which is then used for addressing main memory and is also applied to index a reference/change table. A stored monitor/no monitor signal associated with each segment of virtual memory controls the storage of referenced virtual addresses for monitored segments. Upon a task switch, the stored virtual addresses are applied to index the corresponding T/RAM entries for rapid selective and partial clearing of the T/RAM.

Growing community of inventors

Acton, MA, United States of America

Arthur B Barrow