Honeywell Information Systems Inc.

Arthur A Parmet

Charles W Dawson

Donald R Taylor

John L Curley

C William Dawson

A Reader/Sorter may have an MICR read head, an OMR read head, and two OCR read heads or a combination thereof. A Reader/Sorter Adapter receives characters read by the Reader/Sorter. The characters include data and formatting symbol characters read from a document and control characters generated by the Reader/Sorter. Certain characters may be identified as queue field identifiers (QFI) by the user via software. These are usually the formatting characters. The control characters are identified as pseudo queue field identifiers (PQFI). QFI and PQFI characters are received by a Multiple Device Controller and allow the firmware to identify the length of the data fields, the head from which the characters were received, and any special conditions associated with reading of a data field.

Queue symbol field recovery flags for defining boundaries of one or more

A reader/sorter reads documents which include MICR, OMR and OCR encoded characters. The reader/sorter reads each type of character sequentially at separate read head positions. Character codes read by a particular head address a separate area of address locations in a random access memory which stores equivalent character codes which are used by the data processing system. The random access memory is loaded with the translated character codes, allowing a data processing system to communicate with the reader/sorter.

Apparatus for translation of character codes for application to a data

Information from a document is read by a reader sorter; the information is organized in fields including a transit field which is made up of 8 decimal digits and a check digit. The 8 decimal digits are each multiplied by a predetermined number which depends on the position of the decimal digit in the transit field as indicated by a position counter. Signals indicative of the decimal digit and the position in the transit field are applied to the address terminals of a Programmable Read Only Memory (PROM). Each address location stores the units position of the product of the multiplication of the decimal digit times the predetermined value. A firmware routine stored in a control memory performs the check digit calculation 'on the fly' using the units position of the product from the PROM and certain status bits stored in a scratchpad memory.

Apparatus for calculating a check digit for a stream of data read from a

A system and method for providing a control store arrangement in which a single memory having a plurality of memory locations can be used for storing sequences of microinstructions or scratch pad information. The number of storage locations defining the scratch pad area can be increased or decreased as required by assigning tag addresses to a desired number of scratch pad storage locations when the microinstruction routines are being assembled. In this manner, the locations defining the scratch pad areas can be tailored to the particular system operation to be performed. This eliminates the need for modifying the control store circuits to change the size of the control store scratch pad area.

Control store system and method for storing selectively

A host system includes a microprogrammed processing unit which couples a foreign processing unit to the main memory of the host system. The microprogrammed processing unit also couples to an interface connected to the foreign processor. During operation, the host processor transfers a channel command to the microprogrammed processing unit which is operative under firmware control to perform the various control functions required for initiating a particular job. In this manner, the various parameters and information necessary to dispatch a job of the foreign processor is accomplished expeditiously under the firmware control in response to commands issued by the host processor.

Microprogrammed control of foreign processor control functions

A control store system provides for automatic detection of errors produced by faults in the circuits of the system during both normal and test operations. The system includes a control store and associated address and control circuits. The address and control circuits include a plurality of control address registers and an incrementing circuit. Each storage location of the control store includes a previously generated parity check bit which represents odd parity for the address corresponding to the next sequential storage location. Each of the control registers couples to a parity check circuit. Each time the contents of a storage location within the control store memory are accessed, the parity check circuit of the register receiving the address contents produced by the incrementing circuit is checked for odd parity to determine whether the information accessed is correct and whether the incrementing circuit, the registers, and associated paths are free of faults.

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Waltham, MA, United States of America

Arthur A Parmet