Vital Connect, Inc.

Credo Technology Group Limited

Project Ft, Inc.

Marvell International Limited

Arshan Aga

Farbod Aram

Yun Yang

Steve Fang

Saeed Azimi

Ravi Narasimhan

Haoli Qian

Olivier K Colliou

Junqing Phil Sun

Chi Fung Cheng

Xiang Gao

Hongxin Song

Alexander Chan

Nandakumar Selvaraj

Raymond Liou

Dhwanil Damania

James Bartenslager

Thang Tran

Ni Xu

Nianwei Xing

A system, device and method of calibrating a sensor determine a sensor vector associated with a subject; process the sensor vector; determine a sensor elevation angle as a prediction of the subject's body elevation from a result of processing the sensor vector; and perform calibration using the sensor vector, sensor elevation angle, and a gravity vector.

Sensor calibration considering subject-dependent variables and/or body positions

A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.

Systems and methods for testing jitter tolerance

Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

Scan-chain testing via deserializer port

A method and system for determining a body impedance (Z) of a user are disclosed. The method comprises coupling a sensor device to the user, wherein the sensor device includes at least a first and a second electrode. The method includes applying a voltage signal (V) through a first impedance (Z) to the first electrode and through a second impedance (Z) to the second electrode to produce an output signal. The method includes measuring a differential voltage (V) across the first and second electrodes and calculating the body impedance (Z) using the measured differential voltage (V), the voltage signal (V), the first impedance (Z), and the second impedance (Z).

Method and system for determining body impedance

A system and method for detecting and monitoring core body temperature are disclosed. The system includes a patch device and an electronic module coupled to the patch device. The method includes providing a patch device, coupling an electronic module to the patch device to provide a wearable device, and monitoring core body temperature of a user using the wearable device.

Core body temperature detection device

An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.

PLL with wide frequency coverage

A method and system for determining thermistor resistance have been disclosed. The method comprises providing a temperature sensor network within a wireless sensor device, wherein the temperature sensor network includes a driver device and a receiver device, coupling the driver device to the receiver device using a dual bond wire system, determining at least one output voltage using at least one input current flowing through the dual bond wire system, and determining the thermistor resistance using the at least one output voltage. The system comprises a wireless sensor device including a temperature sensor network that comprises driver and receiver devices, and a dual bond wire system that couples the driver device to the receiver device, wherein at least one output voltage is determined using at least one input current flowing through the dual bond wire system, further wherein the thermistor resistance is determined using the at least one output voltage.

Temperature sensor for measuring thermistor resistance

A method, system, and a computer-readable medium for pairing a wireless sensor device which is associated with a user to a wireless relay device are disclosed. The method, system, and computer-readable medium comprise providing an identification code that includes a network address within the wireless sensor device. The method, system, and computer-readable medium include utilizing an application within a wireless relay device. The application selects the wireless sensor device by using the corresponding identification code, scans for network addresses, and compares the network address to the scanned network addresses. When the network address matches one of the scanned network addresses, the wireless sensor device is paired to the wireless relay device by the application.

Method and system for pairing a sensor device to a user

A method and system for measuring psychological stress disclosed. In a first aspect, the method comprises determining R-R intervals from an electrocardiogram (ECG) to calculate a standard deviation of the R-R intervals (SDNN) and determining a stress feature (SF) using the SDNN. In response to reaching a threshold, the method includes performing adaptation to update a probability mass function (PMF). The method includes determining a stress level (SL) using the SF and the updated PMF to continuously measure the psychological stress. In a second aspect, the system comprises a wireless sensor device coupled to a user via at least one electrode, wherein the wireless sensor device includes a processor and a memory device coupled to the processor, wherein the memory device stores an application which, when executed by the processor, causes the processor to carry out the steps of the method.

Measuring psychological stress from cardiovascular and activity signals

A system and method for powering a wireless sensor device are disclosed. In a first aspect, the wireless sensor device comprises at least two electrodes configured to be attached to a body and at least two leads coupled to the at least two electrodes. The wireless sensor device also includes a system on chip (SoC) coupled to the at least two leads and a portable power source (V) coupled to the SoC. When the at least two electrodes are attached to the body, a difference in resistance is measured between the at least two leads by the SoC and the difference in resistance is utilized by the SoC to enable the portable power source to activate the wireless sensor device.

System and method for powering a wireless sensor device

What is described herein is a technique that includes a clock generator configured to generate a clock signal having a frequency of |f+f|. The technique further includes a mixer configured to input (1) an input signal that includes a desired signal at the frequency fand (2) the clock signal and generate a mixed signal using the input signal and the clock signal. A filter, having a bandpass region that includes the frequency f, is configured to input the mixed signal and generate a filtered signal based at least in part on the bandpass region.

Feedback LNA with image filtering

A voltage controlled oscillator (VCO) includes a first and a second n-type transistor, a first and a second p-type transistor, a first and second capacitive element, a bridge connecting (1) the ground-facing connection of the first n-type transistor and power-facing connection of the first p-type transistor to (2) the ground-facing connection of the second n-type transistor and power-facing connection of the second p-type transistor, a first inductive element, a first capacitor bank, a second inductive element, and a second capacitor bank.

Voltage controlled oscillator

Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator. The method generally includes the steps of coupling an analog storage device and the read channel with an AC-coupling circuit, detecting a baseline or a component of an analog signal at a node downstream from the AC-coupling circuit, and configuring a current device to modify the analog signal in response to detecting the baseline or a component of the analog signal, wherein the current device is coupled to a node downstream from the AC-coupling circuit and upstream from a signal processor configured to operate on the analog signal.

Growing community of inventors

Mountain View, CA, United States of America

Arshan Aga