Sandisk Il Ltd.

Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Arseniy Aharonov

Boris Dolgunov

Evgeny Mekhanik

Asaf Gueta

David Chaim Brief

Yonatan Halevi

Eran Sharon

Yehuda Hahn

Amir Shaharabany

Yoav Markus

Miki Sapir

Inon Cohen

Itshak Afriat

Amir Rozen

Mikhael Zaidman

Rotem Bahar

Oran DeBotton

Tzachy Yizhaki

Raphael Slepon Ben-Yaish

Elad Gola

Roi Jazcilevich

Ivo Faldini

An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that write data having mixed deletion characteristics sequentially to a plurality of data entries of a first physical erase block (PEB) in intermediate storage. The data having the mixed deletion characteristics includes first data having a first deletion characteristic. The processor has programmed instructions that maintain metadata in a plurality of metadata entries in a log. The metadata corresponds to the data having the mixed deletion characteristics. The processor has programmed instructions that identify, using the log, the first data having the first deletion characteristic and evacuate the first data having the first deletion characteristic to a second PEB in main memory.

Log-based storage for different data types in non-volatile memory

Disclosed is an apparatus including a memory system. The memory system includes a controller that assigns a first PEC to a first metablock based on a first number of structures of a memory across which the first metablock is distributed. The controller assigns a second PEC to a second metablock based on a second number of the structures of the memory across which the second metablock is distributed. The controller selects one of the first metablock or the second metablock to be used based on the first PEC and the second PEC.

Systems and methods to optimally select metablocks

The disclosure relates to optimizing a mount process at a data storage device. The storage device communicates with a host using a mount process and mounts a master table, the master table caching translation table pointers associated with a boot partition. The storage device then sends a ready signal to the host indicating that the storage device is ready to receive a boot partition read command from the host. The storage device suspends the mount process for a window of time to receive the boot partition read command and executes the boot partition read command if the boot partition read command is received during the window of time. Accordingly, by caching boot partition pointers in the master table, the mount time of the boot partition is shortened to allow the storage device to send the ready signal earlier and provide the host with earlier access to the boot partition.

Method for fast boot read

A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Timestamp suppression

In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode.

Memory system and method for securing volatile memory during sleep mode using the same ECC module used to secure non-volatile memory during active mode

Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event.

Apparatuses and methods for generating event codes including event source

A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

Block closure techniques for a data storage device

A data storage device includes a non-volatile memory and a controller. A method includes writing an indication of a first error rate of a first set of bits to the non-volatile memory. The first set of bits is sensed from a word line of the non-volatile memory. The word line is sensed to generate a second set of bits in response to a first power-on event being initiated at the data storage device after writing the indication of the first error rate to the non-volatile memory. The method further includes setting a data retention flag in response to a difference between the first error rate and a second error rate associated with the second set of bits satisfying a threshold.

Data retention detection techniques for a data storage device

A data storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

A method for data integrity protection includes receiving items of data for storage in a storage medium. The items are grouped into multiple groups, such that at least some of the groups include respective pluralities of the items. A respective group signature is computed over each of the groups, thereby generating multiple group signatures. An upper-level signature is computed over the group signatures. Groups of the items, the group signatures, and the upper-level signature are stored in respective locations in the storage medium.

Optimized hierarchical integrity protection for stored data

Side channel attacks against a computing device are prevented by combinations of scrambling data to be stored in memory and scrambling the memory addresses of the data using software routines to execute scrambling and descrambling functions. Encrypted versions of variables, data and lookup tables, commonly employed in cryptographic algorithms, are thus dispersed into pseudorandom locations. Data and cryptographic primitives that require data-dependent memory accesses are thus shielded from attacks that could reveal memory access patterns and compromise cryptographic keys.

Memory randomization for protection against side channel attacks

A method for data integrity protection includes arranging data in a plurality of data blocks. A respective block signature is computed over each of the data blocks, thereby generating multiple block signatures. The data blocks and the block signatures in an integrity hierarchy are stored in a storage medium, the hierarchy comprising multiple levels of signature blocks containing signatures computed over lower levels in the hierarchy, culminating in a top-level block containing a top-level signature computed over all of the hierarchy. A modification is made in the data stored in a given data block within the hierarchy. The respective block signature of the given data block is recomputed in response to the modification, and the recomputed block signature is stored in the top-level block for use in verifying a subsequent requests to read data from the given data block.

Systems and methods for providing data integrity protection in a storage medium

A method for data integrity protection includes storing items of data in a plurality of data blocks in a storage medium. Respective block signatures are stored in an integrity structure in the storage medium. A block signature of the given data block is computed in response to a first request to read a first data item from a given data block, and the computed signature is verified against a stored signature read from the integrity structure. The verified block signature is saved in a secure cache. The block signature is recomputed upon receiving a second request to read a second data item, subsequent to the first request, and is verified against the verified block signature in the secure cache. The data item is output from the storage medium in response to verifying the recomputed block signature.

Caching for structural integrity schemes

A method for protecting information in a device includes providing a device with a non-secure hardware domain, a processor having a software-controlled mode of operation, and a secure hardware domain having a secure memory that is inaccessible by the processor when the processor is operating in the software-controlled mode of operation. Data from the non-secure hardware domain is established in the secure hardware domain. Computing operations are executed on the data in the secure hardware domain to produce a result. The secure hardware domain is purged, while retaining the result therein. The result is thereafter returned from the secure hardware domain into the non-secure hardware domain.

Growing community of inventors

Arad, Israel

Arseniy Aharonov