International Business Machines Corporation

Arpith C Jacob

Ravi Nair

Hans Mikael Jacobson

Bruce Martin Fleischer

Alexandre E Eichenberger

Thomas Winters Fox

Tong Chen

Zehra Noman Sura

Jude A Rivers

Daniel Arthur Prener

Olivier H Sallenave

Kevin John Patrick O'Brien

A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the composite VLIW instruction to perform the operation.

Executing a composite scalar-vector VLIW instruction having a repeat field

A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.

Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.

Schedulers with load-store queue awareness

In one embodiment, a computer-implemented method for dispatching a function call includes receiving, at a supervisor processing element (PE) and from an origin PE, an identifier of a target device, a stack frame of the origin PE, and an address of a function called from the origin PE. The supervisor PE allocates a target PE of the target device. The supervisor PE copies the stack frame of the origin PE to a new stack frame on a call stack of the target PE. The supervisor PE instructs the target PE to execute the function. The supervisor PE receives a notification that execution of the function is complete. The supervisor PE copies the stack frame of the target PE to the stack frame of the origin PE. The supervisor PE releases the target PE of the target device. The supervisor PE instructs the origin PE to resume execution of the program.

Dispatching function calls across accelerator devices

A graph analytics appliance can be employed to extract data from a graph database in an efficient manner. The graph analytics appliance includes a router, a worklist scheduler, a processing unit, and an input/output unit. The router receives an abstraction program including a plurality of parallel algorithms for a query request from an abstraction program compiler residing on computational node or the graph analytics appliance. The worklist scheduler generates a prioritized plurality of parallel threads for executing the query request from the plurality of parallel algorithms. The processing unit executes multiple threads selected from the prioritized plurality of parallel threads. The input/output unit communicates with a graph database.

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Dobbs Ferry, NY, United States of America

Arpith C Jacob