Stmicroelectronics International N.v.

Arpit Vijayvergia

Vikas Rana

An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

Circuit and method for on-chip leakage detection and compensation for memories

The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

Memory circuit arrangement for accurate and secure read

An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.

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Bhopal, India

Arpit Vijayvergia