Marvell Israel (misl) Ltd.

Marvell International Limited

Marvellworld Trade Ltd.

Marvell Isreal (m.i.s.l.) Ltd.

Aron Wohlgemuth

Amit Avivi

Gil Levy

Rami Zemach

Yuval Cohen

Amir Roitshtein

Evgeny Shumsky

Adar Peery

Yosef Solt

Lior Valency

Amir Gabai

Michael Moshe

In a method for processing packets in one or more network devices, a first packet is received at the one or more network devices, the first packet being associated with a first bypass indicator. Based at least in part on the first bypass indicator, the first packet, a portion of the first packet, or a packet descriptor associated with the first packet is caused to bypass at least a portion of a first packet processing unit among a plurality of processing units of the one or more network devices, each processing unit being configured to perform a packet processing operation, and not to bypass at least a portion of a second packet processing unit among the plurality of processing units of the one or more network devices.

Switch having dynamic bypass per flow

A plurality of packets are received by a packet processing device, and the packets are distributed among two or more packet processing node elements for processing of the packets. The packets are assigned to respective packet classes, each class corresponding to a group of packets for which an order in which the packets were received is to be preserved. The packets are queued in respective queues corresponding to the assigned packet classes and according to an order in which the packets were received by the packet processing device. The packet processing node elements issue respective instructions indicative of processing actions to be performed with respect to the packets, and indications of at least some of the processing actions are stored. A processing action with respect to a packet is performed when the packet has reached a head of a queue corresponding to the class associated with the packet.

Maintaining packet order in a multi processor network device

A packet being processed by a network device is parsed by a programmable processing unit executing computer readable instructions stored in a non-transitory computer readable storage medium. Parsing the packet includes identifying one or more protocol layers within a header of the packet, identifying respective locations of protocol headers within the header of the packet, and providing the respective identified locations of protocol headers within the header of the packet to a hardware key generator block. A lookup key corresponding to the packet is generated by the key generator block using the respective identified locations. Generating the lookup key includes extracting, using an identified location of a protocol header, one or more fields from the corresponding protocol header. The lookup key is provided to a lookup engine. A lookup operation with respect to the packet is performed by the lookup engine and based on the lookup key.

Packet parsing and key generation in a network device

One or more processing operations with respect to a packet are performed at a packet processing node of a network device, the packet processing node configured to perform multiple different processing operations with respect to the packet. A first accelerator engine is triggered for performing a first additional processing operation with respect to the packet. The first additional processing operation constitutes an operation that is different from the multiple different processing operations that the packet processing node is configured to perform. The first additional processing operation is performed by the first accelerator engine. Concurrently with performing the first additional processing operation at the first accelerator engine, at least a portion of a second additional processing operation with respect to the packet is performed by the packet processing node, the second additional processing operation not dependent on a result of the first additional processing operation.

Processing concurrency in a network device

A processing unit of a packet processing node initiates a transaction with an accelerator engine to trigger the accelerator engine for performing a processing operation with respect to a packet, and triggers the accelerator engine to perform the processing operation. The processing unit attempts to retrieve a result of the first processing operation from a memory location to which a result is to be written. It is determined whether the result has been written to the memory location, and when it is determined that the result has not yet been written to the memory location, the processing unit is locked until at least a portion of the result is written to the memory location.

Aspects of the disclosure provide a packet processing system. The packet processing system includes a plurality of processing units, a ternary content addressable memory (TCAM) engine, and an interface. The plurality of processing units is configured to process packets received from a computer network, and to perform an action on a received packet. The action is determined responsively to a lookup in a table of rules to determine a rule to be applied to the received packet. The TCAM engine has a plurality of TCAM banks defining respective subsets of a TCAM memory space to store the rules. The interface is configured to selectably associate the TCAM banks to the processing units. The association is configurable to allocate the subsets of the TCAM memory space to groups of the processing units to share the TCAM memory space by the processing units.

Architecture for TCAM sharing

Maintaining packet order in a parallel processing network device

Systems and methods are provided for a content addressable memory. A system includes a common memory module configured to store a plurality of entries, ones of the entries being defined by a string of bits. A first parallel compare logic unit is configured to compare a first lookup key against a plurality of entries stored in the memory module in a first memory operation cycle and to output a match indication indicating a match between the first lookup key and the string of bits of an entry from among the plurality of entries. A second parallel compare logic unit is configured to compare, in the first memory operation cycle, a second lookup key against the plurality of entries stored in the memory module and to output a match indication indicating a match between the second lookup key and the string of bits of an entry from among the plurality of entries.

Method and apparatus for content addressable memory parallel lookup

An apparatus having a corresponding method comprises a transmit circuit to transmit data, the transmit circuit comprising a transmit input circuit to input the data, and an address for the data, to the transmit circuit, an encoder to encode the data according to the address for the data, comprising an encode select circuit to select one of a plurality of keys based on the address for the data, and an encoding circuit to encode the data using the key selected by the encode select circuit, and a transmit output circuit to output the encoded data.

System and method for encoding data transmitted on a bus

A multilane communication device and methods for using the multilane communication device. In one embodiment, a physical coding sub-layer module comprising includes multiple data transfer lanes in a port of a multi-lane Ethernet switch for transferring blocks of data between devices in the port. The physical coding sub-layer module further includes a synchronization marker generator for generating synchronization markers to be periodically transmitted over the multiple data transfer lanes. The physical coding sub-layer module further includes a data marker module configured to generate at least two data marker blocks from a respective portion of a synchronization marker and a respective portion of a block of data, and to provide the at least two data marker blocks to respective first and second ones of the multiple of data transfer lanes.

Multilane communication device

An apparatus includes a network port and a switch management processor. The network port receives packets over a network, where the packets include a management packet and a trigger packet. The switch management processor executes a command in selected management packets received over the network when a trigger pattern generated based on the trigger packet matches a bit pattern stored in memory. The bit pattern is stored in the memory during a predetermined period after the management packet is received. The predetermined period is selected based on a desired security level.

Remote network device management

A data processing system includes a memory configured to store data in a plurality of addressable storage spaces thereof, wherein the memory includes a first data port and a second data port, a first functional block configured to access the memory via the first data port to perform a logic operation, and a second functional block configured to access the memory via the second data port to perform soft error scrubbing in the data stored in the memory.

System and method for soft error scrubbing

An apparatus having a corresponding method comprises a memory; a plurality of ports comprising one or more network ports to send and receive data packets and to receive management packets, wherein each of the management packets comprises one or more commands, and wherein the commands comprise one or more of the group consisting of a command to read data from the memory, and a command to write data to the memory, and a central processing unit (CPU) port to transmit packets addressed to a CPU; a forwarding engine to transfer the data packets between the ports according to a forwarding table stored in the memory; a protocol unit to identify the management packets; and a management unit to execute the commands; wherein the management packets bypass the CPU port.

Growing community of inventors

Giv′at-Shmuel, Israel

Aron Wohlgemuth