International Business Machines Corporation

Arnon Amir

Pallab Datta

Dharmendra S Modha

Myron Dale Flickner

Nimrod Megiddo

Tanveer Fathima Syeda-Mahmood

Paul A Merolla

Benjamin G Shaw

Rainer Richter

David Allan Pease

Gal Ashour

David Bruce Koons

Reiner Kraft

Dulce Beatriz Ponceleon

Rathinakumar Appuswamy

Matthew Denesuk

Savitha Srinivasan

Tapan K Nayak

Carlos Hitoshi Morimoto

Brian K Blanchard

Shumin Zhai

David James Beymer

Jianbin Tang

Dragutin Petkovic

Karen Wolfe Brannon

Antonio Jose Jimeno Yepes

Sangeeta T Doraiswamy

David J Berg

Malcolm Slaney

Jeffrey Alan Kusnitz

Wayne Isami Imaino

Philipp Herget

Hartmut Penner

Prasad Manikarao Deshpande

Alexander Andreopoulos

Brian Taba

Ran D Zilca

Harald Seipp

Gregory Fraser Russell

James Clinton Spohrer

Michael Rodeh

Vladimir Zbarsky

Carlton Wayne Niblack

Giridharan R Iyengar

Norman Jerome Pass

Douglas Warren McDavid

Steven Carlyle Ihde

Alon Efrat

Tanveer Fathima Syeda-Mahood

Systems for distributed, event-based computation are provided. In various embodiments, the systems include a plurality of neurosynaptic processors and a network interconnecting the plurality of neurosynaptic processors. Each neurosynaptic processor includes a clock uncoupled from the clock of each other neurosynaptic processor. Each neurosynaptic processor is adapted to receive an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs. Each neurosynaptic processor is adapted to compute, for each clock value, an output based on the inputs associated with that clock value. Each neurosynaptic processor is adapted to send to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

Distributed, event-based computation using neuromorphic cores

Core utilization optimization by dividing computational blocks across neurosynaptic cores is provided. In some embodiments, a neural network description describing a neural network is read. The neural network comprises a plurality of functional units on a plurality of cores. A functional unit is selected from the plurality of functional units. The functional unit is divided into a plurality of subunits. The plurality of subunits are connected to the neural network in place of the functional unit. The plurality of functional units and the plurality of subunits are reallocated between the plurality of cores. One or more unused cores are removed from the plurality of cores. An optimized neural network description is written based on the reallocation.

Core utilization optimization by dividing computational blocks across cores

Weighted population code in neuromorphic systems is provided. According to an embodiment, a plurality of input values is received. For each of the plurality of values, a plurality of spikes is generated. Each of the plurality of spikes has an associated weight. A consumption time is determined for each of the plurality of spikes. Each of the plurality of spikes is sent for consumption at its consumption time.

Efficient generation of stochastic spike patterns in core-based neuromorphic systems

Hardware optimization of neural networks is provided. In various embodiments, an output-induced receptive field of each of a plurality of layers of a neural network is determined. From each of the plurality of layers any portions of their respective input that falls outside their respective output-induced receptive field are trimmed. For each of the plurality of layers, a plurality of mappings of the layer to physical neurosynaptic cores are determined. A mapping is determined having a minimum total number of cores required for the neural network based on the plurality of mappings.

Optimized partitioning of multi-layer networks in core-based neurosynaptic architectures

Embodiments of the invention provide a method comprising maintaining a library of one or more compositional prototypes. Each compositional prototype is associated with a neurosynaptic program. The method further comprises searching the library based on one or more search parameters. At least one compositional prototype satisfying the search parameters is selected. A neurosynaptic network is generated or extended by applying one or more rules associated with the selected compositional prototypes.

Compositional prototypes for scalable neurosynaptic networks

Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.

Graph partitioning and placement for multi-chip neurosynaptic networks

Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.

Detection, tracking and recognition on networks of digital neurosynaptic cores

Embodiments of the invention provide a method for mapping a bipartite graph onto a neuromorphic architecture comprising of a plurality of interconnected neuromorphic core circuits. The graph includes a set of source nodes and a set of target nodes. The method comprises, for each source node, creating a corresponding splitter construct configured to duplicate input. Each splitter construct comprises a first portion of a core circuit. The method further comprises, for each target node, creating a corresponding merger construct configured to combine input. Each merger construct comprises a second portion of a core circuit. Source nodes and target nodes are connected based on a permutation of an interconnect network interconnecting the core circuits.

Mapping graphs onto core-based neuromorphic architectures

One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a metadata analysis unit for analyzing metadata information associated with one or more portions of an adjacency matrix representation of the neural network, and a mapping unit for mapping the one or more portions of the matrix representation onto the neurosynaptic substrate based on the metadata information.

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

In one embodiment, a computer program product for optimizing core utilization in a neurosynaptic network includes a computer readable storage medium having program instructions embodied therewith, where the computer readable storage medium is not a transitory signal per se, and where the program instructions are executable by a processor to cause the processor to perform a method including identifying, by the processor, one or more unused portions of a neurosynaptic network, and for each of the one or more unused portions of the neurosynaptic network, disconnecting, by the processor, the unused portion from the neurosynaptic network.

Optimizing core utilization in neurosynaptic systems

Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.

Optimizing neurosynaptic networks

In one embodiment, a data storage system includes a tape drive configured to: write a plurality of files to a first partition of a magnetic recording tape; and write an index to a second partition of the magnetic recording tape, the index including information about locations of data of the plurality of files in the first partition of the magnetic recording tape. In another embodiment, a magnetic recording tape includes: a plurality of files to written to a first partition of the magnetic recording tape using a tape drive; and an index written to a second partition of the magnetic recording tape using the tape drive, the index including information about locations of data of the plurality of files in the first partition of the magnetic recording tape.

File index, metadata storage, and file system management for magnetic tape

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Saratoga, CA, United States of America

Arnon Amir