Google Inc.

Aeluros, Inc.

Texas Instruments Corporation

Intel Corporation

Zeevo, Inc.

Arnold Robert Feldman

Hae-Chang Lee

Marc Loinaz

Michael J Buckley

Shahriar Rabii

Andrew Keith Joy

Benjamin Joseph Mossawir

Lynn Bos

Paul Swirhun

Dennis Gee-Wai Yee

Paul J Husted

Jiang Zhu

Jaime Lien

Cheng-Yi Andrew Lin

Roy Michael Bannon

Leesa Marie Noujeim

Maryam Tabesh

David J Weber

Arnd Geis

Jian Wang

Leesa Marle Noujelm

Dave Moloney

Various arrangements for using a positioning tag to facilitate control of a smart home device are presented herein. A communication sessions can be established between a control device and a positioning tag via a first device-to-device communication protocol. In response to a trigger event indicative of a user desiring to control the separate smart home device being detected, a positioning enablement message can be transmitted to the positioning tag via the first device-to-device communication protocol. A signal used for positioning is transmitted by the positioning tag using a second device-to-device communication protocol. Based on the received signal via the second device-to-device communication protocol, an interface that controls the smart home device is activated.

Facilitating smart device control using positioning tags

Devices are provided that include radar circuits arranged to send and receive radar signals that can be used to, for example, detect gestures performed in the vicinity of the device. Arrangements of the circuits and associated antennas allow for the device to have no bezel or a minimal bezel.

Human and gesture sensing in a computing device

This document describes techniques and systems that enable battery state estimation. The techniques and systems may be used to determine a shut-down voltage for a battery of an electronic device. Additionally or alternatively, the techniques and systems may be used to determine a state-of-charge of the battery, which may be determined relative to the shut-down voltage. The techniques and systems use current or expected conditions at the battery to estimate the battery state. These techniques can allow the electronic device to dynamically set a shut-down voltage, rather than using a fixed shut-down voltage over the life of the electronic device. The dynamically set shut-down voltage can provide a low margin, and therefore a greater portion of battery capacity, when operating in good conditions and provide a relatively large margin that is sufficient for poor conditions.

Battery state estimation

A phased-array antenna includes an antenna layer of a stacked printed circuit board, a ground plane layer of the stacked printed circuit board spaced apart from the antenna layer, and a first dielectric layer of the stacked printed circuit board disposed between and in opposed contact with the antenna layer and the ground plane layer. The antenna layer includes an associated metal patch pattern defined by a series of slots. The stacked printed circuit board defines a thickness extending between a top end of the stacked printed circuit board and a bottom end of the stacked printed circuit board. The phased-array antenna includes a series of ground vias extending between the top and bottom ends of the stacked printed circuit board. The ground vias are configured to suppress surface waves propagating across the stacked printed circuit board.

Suppression of surface waves in printed circuit board-based phased-array antennas

A method including identifying clusters of antenna elements of a phased array antenna. For each cluster of antenna elements, the method includes identifying a reference antenna element of the cluster of antenna elements and identifying pairs of calibration antenna elements of the cluster of antenna elements. For each pair of calibration antenna elements, the method includes executing a calibration routine configured to determine a calibration adjustment for each antenna element of the pair of calibration antenna elements based on the reference antenna element. The method also includes determining a leveling adjustment for each antenna element of the phased array antenna. The method further includes adjusting the element gain and the element phase of each antenna element of the phased array antenna based on the corresponding leveling adjustment to equalize a transmission gain and a transmission phase of each signal path of the phased array antenna.

Phased array antenna calibration

A circuit includes a power amplifier that includes a transformer having a primary winding and a secondary winding. The secondary winding has a first terminal and a second terminal. The circuit also includes a transmit/receive switch electrically connected between the first terminal of the secondary winding and electrical ground. The second terminal of the secondary winding is electrically connected to an antenna that transmits signals based on an output of the power amplifier and to an input of a second amplifier that is also connected to the antenna. The transmit/receive switch selectively switches between a closed position that connects the secondary winding to ground in a transmit mode and an open position that disconnects the secondary winding from ground in a receive mode.

Power amplifier with ground switch for transmit/receive functionality

A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.

Phase shifter chip radio frequency self-test

A phased array antenna system includes an array of antennas having first antenna and second antennas disposed equidistantly from a third antenna. The first antenna is associated with a first gain and a first phase and the second antenna is associated with a second gain and a second phase. The first antenna receives a first reference signal corresponding to a calibration reference signal transmitted by the third antenna, and the second antenna receives a second reference signal corresponding to the calibration reference signal transmitted by the third antenna. The second receiver module is configured to adjust the second gain and the second phase associated with the second antenna to match the first gain and the first phase associated with the first antenna by comparing the first reference signal received by the first antenna with the second reference signal received by the second antenna.

Phased array antenna self-calibration

A phased-array antenna assembly includes an antenna board stack, a radome configured to cover the antenna board stack, and a casing configured to support the antenna board stack. The antenna board stack includes a central core, a bottom antenna unit defining a bottom thickness between a bottom surface of the central core and a bottom end of the antenna board stack, and a top antenna unit defining a top thickness between a top surface of the central core and the top end of the antenna board stack that is substantially equal to the bottom thickness. The bottom antenna unit includes two spaced apart bottom metal layers each associated with a different distance from the axis of symmetry. The top antenna unit includes two spaced apart top metal layers each associated with a corresponding one of the distances from the axis of symmetry associated with the bottom metal layers.

Balanced multi-layer printed circuit board for phased-array antenna

The method includes selecting, by control hardware, a first output from a phased locked loop, sending, by the control hardware, the first output from the phased locked loop to a first device under test and a second device under test, and adjusting, by the control hardware, a first phase rotator connected to the first device under test to a first rotator phase value of zero; determining a collection of phase detector values of a phase detector connected to the second device under test by adjusting a second phase rotator connected to the second device under test to sweep through a phase range and measuring the phase detector values of the phase detector; determining a phase detector gain of the phase detector by averaging the collection of phase detector values and storing, by the control hardware, the phase detector gain in memory hardware.

A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h=h+h; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Clock data recovery system

Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.

Compensating a two stage amplifier

A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Growing community of inventors

San Francisco, CA, United States of America

Arnold Robert Feldman