International Business Machines Corporation

Arnold Reisman

Melvin Berkenblit

Ernest Bassous

Robert O Lussow

Asit Kumar Ray

Billy L Crowder

Kyu C Park

See Ark Chan

Frank Benjamin Kaufman

Paul S Ho

Lawrence Kuhn

Takeshi Takamori

Carlton M Osburn

Howard Hyman Taub

Charles J Merz, Iii

Frederick Hochberg

Peter Pleshko

Stanley Zirinsky

Marvin B Skolnik

Dennis C Green

Tung-Sheng Kuan

Moshe Balog

See-Ark Chan

Iwao Ohdomari

Uwe Koster

Carl Altman

Joan B Landermann

A mirror array light valve is described comprising a transparent substrate, a plurality of post members arranged in a regular array on said substrate, and a plurality of deflectable square, rectangular, hexagonal or the like light-reflecting elements arranged in a regular array on said post members such that a post member is positioned under a corresponding corner of each element; methods for making the mirror array light valve are also described.

Mirror array light valve

A heat dissipating system for cooling circuit chips or modules is described. The disclosed system includes circuit chips or modules which are vertically mounted, a gas at an elevated pressure being contained within an encased module for providing an enhanced thermal coupling between the chips or modules contained therein, and the walls of the encased module, whereby heat removal from the chips or modules is increased. This enhanced thermal coupling is combined with a reduction in the temperature of the walls of the encased modules so as to reduce the thermal resistance between the surrounding gas and the chips or modules to be cooled, whereby heat removal from the circuit chips or modules is substantially increased.

Vertical wall elevated pressure heat dissipation system

An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer integrated circuit devices. Such interconnecting members are useable to produce field effect transistor type devices.

Semiconductor integrated circuit interconnections

An elevated pressure reactor apparatus for oxidizing or annealing specimens of the type including a reaction tube for containing the specimen surrounded by a heating furnace and enclosed in a pressure chamber, the apparatus incorporating a unique single gas flow feature, an improved multi-element furnace structure, a retrograde closure for the reaction tube to prevent gas flow back from the pressure chamber, a magnetically connected driving mechanism for a specimen support boat, and concentric gas entrance and exit tubes wherein exiting gas pre-heats the entering gas.

Single gas flow elevated pressure reactor

Doped polysilicon silicide semiconductor integrated circuit

Plasma oxidation of the surface of a substrate which surface does not face towards the plasma is achieved by placing the substrate perpendicular to the plasma in a region at a pressure of at least about 10 mtorr.

Plasma oxidation

Methods and resulting structures for thermally stable metal/silicon contacts are described. The resulting contacts are aluminum which is alloyed with at least one noble metal from the group of Pd and Pt wherein at least one region of the contact is further alloyed with silicon.

Metal/silicon contact and methods of fabrication thereof

Uniform growth of oxide at low temperature can be performed in a plasma environment by positioning the substrates on which the oxide is to grow outside of the plasma area and independently supplying heat to the substrates in the presence of controlled oxygen pressure.

Semiconductor plasma oxidation

There are provided quaternary etchants comprising ethylenediamine, pyrocatechol, water and a diazine as catalyst for the etching of polycrystalline or single crystal silicon over a wide temperature and etch rate range. The etchants provide residue free dissolution, and have etch rates which are essentially unchanged when exposed to oxygen. The etch rate of the etchants can be modulated by the change in concentrations of water and/or pyrocatechol. There is also provided a method for etching polycrystalline or single crystal silicon using the etchants of this invention.

Method for etching silicon and a residue and oxidation resistant etchant

A method for controlling the etch rate of a quaternary etchant comprising ethylene diamine, water, pyrocatechol and a diazine. The etching rate is catalyzed and controlled by controlling the amount of the diazine present in the etchant. A method for the controlled etching of silicon is also disclosed.

Method of controlling silicon wafer etching rates-utilizing a diazine

The invention provides a method for forming a protective silicon carbide (SiC) film on a silicon (Si) substrate. The method permits the formation of silicon carbide on the Si substrate on all surfaces simultaneously. The process is highlighted in that the silicon substrate to be coated is placed in a susceptor having tantalum carbide surfaces and which has a high purity ambient. The substrate is heated at a temperature about 1250.degree. C to remove native SiO.sub.2 from its surface. The system is then cooled to a temperature of about 900.degree. C and methane is added for about 30 minutes to thereby deposit a layer of carbon which is further reacted with the Si substrate at 1250.degree. C to form a smooth, pin hole free SiC film. SiC layers are also formed by a one step reaction in which methane is reacted directly with Si at 1250.degree. C.

Method for forming smooth self limiting and pin hole free SiC films on Si

A method for etching at least one aperture having a defined crystallographic geometry in single crystals which includes masking the crystal to protect predetermined portions thereof from being etched, and then anisotropically etching with a mixture of sulfuric acid and phosphoric acid.

Process for etching holes

A process for the fabrication of a deformographic storage display tube (DSDT) target in which a wafer of silicon or other etchable material is used (1) as a temporary support during the generation of the active region of the target and (2) as a supporting structure for the completed target. The DSDT target structure comprises a reflection layer on a dielectric layer supported in turn on a silicon or other etchable material wafer, the wafer being etched off at its back side to expose the dielectric layer while providing an outer frame support structure made of the wafer around the edge, with the dielectric layer being etched to form pillars of the dielectric on the backside of the reflection layer, whereby the dielectric pillars enable a deformation action to occur in the region between the pillars. An inner frame support structure comprised of a similarly etched wafer, a dielectric layer and a secondary electron emission layer is fitted against the bottoms of the pillars and bonded to the outer frame support structure, thereby forming the completed target.

Method for fabricating a DSDT target

An in situ process is disclosed for fabricating gas discharge display panels in a sequential seal, bake-out and backfill mode of operation. The single thermal cycle process involves placing unassembled panel parts in a controlled gas ambient furnace system with required seal frame, evacuating said furnace and backfilling with an appropriate ambient atmosphere to an appropriate pressure while heating the furnace. During the heating, the furnace is repeatedly evacuated to moderate vacuum and refilled to some predetermined pressure. The furnace is heated to just above the glass transition temperature of the seal frame in this evacuate-refill mode, then held for some time to achieve outgassing of both panel parts and furnace chamber. Thereafter, the furnace chamber is refilled to one atmosphere and further heated to complete the sealing of the panel. The panel is then cooled to approximately 300.degree. C, still under one atmosphere, after which the evacuate-refill cycle is continuously repeated as the temperature is lowered down to the temperature of tip-off using the refill gas for the pressurization. The panel is refilled to an appropriate pressure at elevated temperature such that at room temperature the pressure is the desired pressure and the panel is tipped off. The process of successive evacuations and backfillings at the appropriate portions of the cycle are highly desirable for cleaning of the panel parts via contaminant dilution.

Gas discharge display panel fabrication

A process for controlling the softening point and for providing a preselected softening point of solder glass which comprises bubbling oxygen-containing gas through a homogeneous melt of a solder glass containing copper oxide at a temperature and oxygen partial pressure predetermined to provide the desired preselected softening point of the solder glass and for a time sufficient to achieve equilibrium of the reaction Cu.sub.2 O+1/2O.sub.2 .revreaction.2CuO.

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Yorktown Heights, NY, United States of America

Arnold Reisman