Cadence Design Systems, Inc.

Arnold Jean Marie Gustave Ginetti

Taranjit Singh Kukal

Xavier Alasseur

Balvinder Singh

Chayan Majumder

Jean-Noel Pic

Madhur Sharma

Sutirtha Kabir

Gerard Tarroux

Devendra Ramakant Deshpande

Steven Roberts Durrill

Hitesh Marwah

Nikhil Gupta

Steve Song Lee

Vikrant Khanna

Fabien Campana

Ritabrata Bhattacharya

Tapan Kumar Singh

Vikas Aggarwal

Preeti Chauhan

Jean-Noel Francois Philippe Marie Pic

Harpreet Singh

Diwakar Mohan

Jagdish Lohani

Harmohan Singh

Embodiments included herein are directed towards a method for use in an electronic design. The embodiments may include causing, at a graphical user interface, a display of a portion of the electronic design. The method may further include determining a location of a mouse cursor at the graphical user interface. The method may also include automatically displaying at the graphical user interface one or more shapes associated with a current fabric. The method may additionally include automatically performing a cross fabric shape query associated with the location of the mouse cursor. Furthermore, the method may include automatically displaying one or more cross fabric shapes at the graphical user interface.

Cross-querying between distributed interactive applications

Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at the electronic design layout displayed on the graphical user interface, based upon at least in part, the source topology.

System and method for routing in an electronic design

Embodiments include herein are directed towards a method for electronic circuit design is provided. Embodiments may include allowing, at a graphical user interface, a user to initiate a co-design mode associated with an electronic design. Embodiments may further include allowing, at the GUI, the user to select a shape to trace connectivity from. Embodiments may also include tracing the connectivity of the shape across one or more overlaps and identifying one or more pins associated with the connectivity. Embodiments may further include determining a correct pin from an instance associated with the connectivity and displaying the connectivity at the GUI.

System and method for tracing nets across multiple fabrics in an electronic design

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with real-time modeling. An electronic design may be prepared for an analysis that programmatically sweeps across multiple values of a new parameter for multiple instances in the electronic design. The analysis may be performed on the electronic design at least by adding the new parameter to the analysis engine and by sweeping the new parameter across the multiple values to generate an analysis result. The electronic design may then be updated based at least in part upon the analysis result.

Method, system, and computer program product for characterizing electronic designs with real-time modeling

An approach is described for a method, system, and product for detection of contours for data pads of a device having a free form contour, clustering integrated circuit pads and data pads, performing any angle routing based on a contour angle, and performing resistance balancing. For example, data pads of a display device having one or more curved contours (e.g. data pads arranged on an arc) are identified. Corresponding data pads and integrated circuit pads are then grouped together for routing interconnections and subsequently routed using any angle routing instead of merely routing interconnections with turns having 90-degree or 45-degree angles. Finally, the routed interconnects may be further refined/modified to balance resistances of the interconnections.

Method, system, and product to efficiently route interconnections following a free form contour

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view

Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the simplified electronic design may then be characterized using at least the characterization input.

Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques

Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is connected to an instance of the second electronic design. In response to the input, one or more co-design modules render a representation of the first layout with emphasized circuit components in the first design fabric and the second design fabric, wherein the one or more co-design modules are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system.

Methods, systems, and computer program product for interactively probing a multi-fabric electronic design

Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.

Methods, systems, and computer program product for reducing interferences and disturbances in a multi-fabric electronic design

Disclosed are methods, systems, and articles of manufacture for determining layout equivalence between a plurality of versions of a single layout of a multi-fabric electronic design. These techniques identify a first version and a second version of a layout of an electronic design that spans across multiple design fabrics. One or more collaborative comparator modules are executed to determine whether the first version is identical to or different from the second version of the layout. These techniques further modify the first version or the second version of the layout with discrepancy annotation.

Methods, systems, and computer program product for determining layout equivalence for a multi-fabric electronic design

Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view

The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact of the edit on the die layout and in response to the edit, mirroring the edit at the die layout.

System, method and computer program product for design rule awareness associated with die and package electronic circuit co-design

Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design

Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design

The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.

Growing community of inventors

Antibes, France

Arnold Jean Marie Gustave Ginetti