Trw Limited

USA As Represented by Secretary of the Navy

United States of America As Represented by the Secretary of the Air Force

Northrop Grumman Systems Corporation

Arnold H Silver

Hugo W Chan

Robert D Sandell

Dale J Durand

Bruce J Dalrymple

Quentin P Herr

Andrew Donovan Smith

Randy Wayne Simon

Richard R Phillips

Gregory Steven Lee

Michael Jansen

Jane J Yang

Mark Winslow Johnson

Jaroslava Z Wilcox

James M Murduck

Szutsun S Ou

William W Simmons

Michael Leung

James E Zimmerman

Peter L McAdam

Charles M Jackson

Hugo W K Chan

Eugene L Dines

Susanne L Thomasson

A superconducting self-clocked complementary SFQ logic family. The basic element of the circuit is a plurality of Josephson junctions and a control inductance coupled across a pair of voltage rails. An important aspect of the invention relates to the use of voltage biasing for the Josephson junctions, which provides several benefits. First, voltage biasing eliminates the need for biasing resistors as used in constant current mode devices. Such biasing resistors are known to be the dominant source of power dissipation in such logic circuits. Elimination of the biasing resistors thus reduce the power dissipation to the lowest possible value to that of the power dissipation of the switching devices themselves. In addition, the voltage biasing takes advantage of the voltage to frequency relationship of Josephson junctions and automatically establishes a global clock at the Josephson frequency without the need for extra circuitry; thus increasing the practical clock rate. In addition, elimination of extra clock circuitry increases the potential circuit density. The logic superconducting digital logic family in accordance with the present invention includes devices which perform logic functions such as, AND, OR etc. as well as non-logic functions, such as a shift register function.

Self-clocked complementary logic

A superconductor circuit ( ) for providing active timing arbitration between SFQ pulses. The superconductor circuit ( ) includes a first superconducting transmission line ( ) having at least one inductor ( ) for transmitting first input pulses, and a second superconducting transmission line ( ) having at least one inductor ( ) for transmitting second input pulses that are correlated to the first input pulses. The first and second superconducting transmission lines ( ) are coupled together in order to generate a flux attraction between the first and second input pulses for reducing relative timing uncertainty.

Active timing arbitration in superconductor digital circuits

High temperature superconductive (HTS) integrated circuits can be fabricated in three ways according to the invention. First, a planar multiple layer HTS integrated circuit is fabricated using multiple HTS layers. The layers include altered regions which have been bombarded using ion implantation to destroy superconductivity of the altered regions without interrupting the lattice structure of the altered regions. Second, a planar multiple-layer HTS integrated circuit includes upper and lower HTS layers, each including central and opposing regions. A first implant energy is used to destroy superconducting properties of the opposing regions of the lower HTS layer without interrupting the lattice structure. A second implant energy is used to destroy superconducting properties of a top portion of the central region to define a contact. Third, a HTS integrated circuit is formed from a single HTS layer using three ion implantation steps and ions having first, second and third energies and range.

Planar high temperature superconductive integrated circuits for using ion implantation

A control scheme for operating an oscillator/counter A/D converter so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator. The voltage controlled oscillator receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit that, depending on a gate control signal, either blocks the pulses or passes the pulses to either an increment or a decrement port of a digital counter. When the pulses are passed by the gate circuit, the counter circuit accumulates the pulses during a sampling period. The sampling period covers a range of gate control pulses so that the accumulation of pulses defines consecutive on/off periods of the gate control signal. The scheme provides for frequency conversion and eliminating or minimizing the amount of DC response present in the digital output signal.

Direct digital downconverter and method for converting an analog signal to a digital signal

A control scheme for operating an oscillator/counter A/D converter (10) so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (10) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (12). The voltage controlled oscillator (12) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (14) that either passes or blocks the pulses depending on a gate control signal. When the pulses are passed by the gate circuit (14), a counter circuit (16) accumulates the pulses during a sampling period. The sampling period covers a range of gate control pulses so that the accumulation of pulses defines consecutive on/off periods of the gate control signal. Each time the gate control signal passes the pulses from the variable controlled oscillator (12), the converter (10) effectively performs a bit multiplication that gives the frequency conversion.

Direct digital downconverter based on an oscillator/counter

A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18. In another embodiment, the method includes the steps of: depositing in-situ a superconductive layer 12 on a base layer 14; depositing in-situ a conductive layer 22 on the superconductive layer 12 to form a bi-layer 24; patterning an interconnect region 16 on the bi-layer 24; and converting the interconnect region 16 of the bi-layer 24 to a resistor material region 18.

Method of fabricating a low-inductance in-line resistor for

A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.

Superconductor hetero-epitaxial josephson junction

A correlated superconductor single flux quantum oscillator-counter analog-to-digital (A/D) converter has a superconducting quantum interference device (SQUID) quantizer 20 with two Josephson junctions 24 and 26, each connected to a digital sampling and counting circuit with synchronized timing to increase the sampling rate or the bit resolution of the A/D converter. In a preferred embodiment, a plurality of SQUID quantizers 60 . . . 72 each with two Josephson junctions 74 . . . 88 are connected to a counter structure with precisely synchronized timing to further increase the sampling frequency and/or the bit resolution. A counter structure preferably comprises multiple rows 218, 240, 254 of single flux quantum flip-flops 220 . . . 234, 242 . . . 248, 256, 258 and parallel-serial converter/shift registers 236 250, 260 to produce an output digital data stream in serial form.

Correlated superconductor single flux quantum analog-to-digital converter

Planar in-line resistors for superconductor circuits

A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . . 70f are arranged in a plurality of columns and rows with column select inputs 72, 74 and row select inputs 76, 78 and 80. Digital-to-analog converters 86 and 88 are preferably provided to convert a binary digital input into the analog control current I.sub.con, the magnitude of which is designed to cross a number of current threshold boundaries corresponding to the digital input. A plurality of single flux quantum counters 112 and 114 are preferably connected to count the number of Josephson pulses from the SQUID memory cells 70a, 70b, . . . 70f to generate a count of the pulses as the memory output. In a preferred embodiment, the memory outputs from the single flux quantum counters 112 and 114 are fed back into the input digital-to-analog converters 86 and 88, respectively, to form a non-destructive readout.

Multi-state Josephson memory

A method of in-situ fabrication of a Josephson junction having a laminar structure, the method comprising the steps of: (1) etching a planar substrate to yield a first planar segment, a second planar segment and a ramp segment, the ramp segment connecting the two planar segments at an angle thereto and the substrate having a constantly-decreasing thickness in the ramp segment; (2) depositing a first superconductive layer on the substrate; (3) depositing a non-superconductive layer on the first superconductive layer; and (4) depositing a second superconductive layer on the non-superconductive layer, wherein both the first and second superconductive layers, and the non-superconductive layer are epitaxial with a c-axis in a direction substantially normal to the plane of the first and second planar segments, and the layers are of substantially uniform thickness in the three segments.

In-situ fabrication of a superconductor hetero-epitaxial Josephson

A multi-layer superconductive interconnect structure includes a first multi-layer substrate with a first superconducting layer (SL) deposited on a first epitaxial substrate and a first glue dielectric layer (GDL) on the first SL. A second multi-layer substrate includes a second SL deposited on a second epitaxial substrate and a second GDL on said second SL. The first GDL and the second GDL are clamped and cured together to form a composite substrate.

Multi-layered superconductive interconnects

A high frequency receiver detects and downconverts 50-1,000 GHz radio frequency signals using a receiver consisting of a lens and planar antenna, pre-amplifier, mixer, local oscillator, and IF-amplifier. The insulating dielectric lens is used to focus terahertz radio frequency signals onto the thin film antenna. The preamplifier amplifies these faint signals so that they can be downconverted into an intermediate frequency by the mixer and local oscillator. The mixer is a dual port device which provides isolation of the local oscillator and input signal to avoid saturation of the preamplifier. The IF amplifier boosts the amplitude of the downconverted IF signal produced by the mixer.

Integrated superconductive heterodyne receiver

A high-speed gamma pulse suppression circuit employing a frequency discrimination and sampling technique for elimination of gamma induced noise from semiconductor infrared detectors. The gamma pulse suppression circuit includes a high pass filter for separating high-frequency gamma induced pulses from a detector signal and a gamma pulse detector for detecting the gamma induced pulses. The gamma pulse suppression circuit is connected in parallel with a detector readout circuit such that the suppression circuit causes the readout circuit to discard samples of the detector signal in which gamma induced pulses are detected. The gamma pulse suppression circuit provides effective and efficient real time gamma pulse suppression by completely eliminating the detected gamma pulses from the detector signal, while preserving the quality of the signal.

High-speed gamma pulse suppression circuit for semiconductor infrared

A cryogenic device comprises a vessel to be maintained at a cryogenic temperature. The vessel is mounted on a storage tank in a pressure Eight relationship. Cryogenic fluid under pressure is forced into the vessel through a transfer tube. The temperature in the vessel is controlled by flow of cryogenic fluid through the vessel. A throttle valve in a line leading from the cryogenic vessel regulates the cryogenic fluid flow in relation to a sensed temperature in the vessel.

Growing community of inventors

Rancho Palos Verdes, CA, United States of America

Arnold H Silver