Cadence Design Systems, Inc.

Vlsi Technology, Inc.

Vsli Technology, Inc.

Arnold Ginetti

Jean-Noel Pic

Taranjit Singh Kukal

Francois Silve

Vikas Kohli

Gerard Tarroux

Steven Roberts Durrill

Randy Bishop

Balmukund K Sharma

Mossaddeq Mahmood

Gilles S C Lamant

Hitesh Marwah

Madhur Sharma

Jean-Michel Fernandez

Donald John O'Riordan

Amit Kumar

Devendra Ramakant Deshpande

Kenneth Ferguson

Mark Steven Hahn

Rajan Arora

Yuan-Kai Pei

Athanasius W Spyrou

Jim Newton

Theodore Alan Paone

Christopher H Kingsley

Roland Ruehl

Karun Sharma

Regis R Colwell

Chayan Majumder

Yu-Chi Su

Robert D Shur

Jeffrey Markham

Thomas J Schaefer

Balvinder Singh

Chung-Do Yang

Harish Kriplani

Nikhil Gupta

Vikrant Khanna

David J Mallon

Chandra Prakash Manglani

Athanasius Spyrou

Gilles Lamant

Fabrice Raymond Morlat

Sunil Prasad Todi

Claire Nauts

Andrew David Beckett

Jean-Charles Giomi

Jean-Marc Bourguet

Christophe Gauthron

Jose A Martinez

Ritabrata Bhattacharya

Laurent Robert Chouraki

Steven Riley

Tyler James Lockman

Abhay K Agarwal

Jean-François Alain Lepère

Mandalagiri Chandrasekhar

Abhishek Dabral

Francedillaois Silve

Olivier Arnaud

Alexander B Wong

Philippe Bourdon

Stephane Berger

Thomas Wilson

Khalid ElGalaind

Thomas Jordan

Carole Perrot

Naser Awad

Jean-Michel Fernandes

Gerrard Tarroux

Philippe Troin

Srihari Sampath

Disclosed is a method and system for visualizing schematic changes for an electronic design, where multiple schematic view interfaces are provided such that a first schematic interface displays an older schematic version and a second schematic interface displays a newer schematic version. Coordination is performed between the multiple schematic views such that an element within any of the first or second schematic views is appropriately highlighted based upon a user input.

Method and system to facilitate schematics for an electronic design

Disclosed is an improved approach to implement electronic designs by performing altitude-based re-layering for I/Os. The altitude-based die stack layers allows N number of die stack layers corresponding to the actual altitudes of the I/Os in the design.

Method and system to implement altitude based I/O re-layering for electronic and photonic designs

Disclosed is an improved approach to identify and visualize relevant changes that are made between an earlier schematic and an updated schematic. Both the old schematic and the updated schematic are presented into separate interface windows in conjunction with the layout design. Any changes between the schematics that are pertinent to the electronic design can be highlighted within the interface windows to permit the layout designer to properly appreciate any changes that are relevant to the layout.

Method and system to facilitate review of schematics for an electronic design

Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques execute a sequence of instructions to identify at least a layout or a portion thereof and identify a plurality of layout devices in the layout or the portion thereof. These techniques further generate a figure group at least by enclosing the plurality of layout devices within a boundary for the figure group. These techniques may modify layout devices in a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.

Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns

The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may further include allowing a user to insert, at the graphical user interface prior to signoff, a copper pillar bump or solder bump on at least a portion of the layout based upon, at least in part, the determined expected thermal or centrifuge force manufacturing variation. Embodiments may further include displaying the copper pillar bump or the solder bump on the layout at the graphical user interface.

System, method, and computer program product for displaying bump layout for manufacturing variations

A system and method for an interactive circuit layout design that provides spatially adaptive overlay indicative of parametric properties. A physical layout of an electrical circuit product is rendered on a display. At least one net of the physical layout is delineated into a plurality of net segments each having at least one physical property parametrically specified in a value therefor. For each net segment, a corresponding segment indicator is selectively rendered on the display, adaptively positioned and spatially mapped to the net segment corresponding thereto as a symbolic surrogate for the corresponding net segment within the physical layout. Selection of a net segment actuates determination of a behavior of the electrical circuit product during an operation consistent with an electrical response of the corresponding net segment. Editing of a net of the physical layout delineates a plurality of updated net segments for the edited net exclusive of other nets.

Electronic circuit design editor with overlay of layout and schematic design features

Disclosed herein are embodiments for generating hierarchical rotating pcells (parametrized cells) design from a user provided static hierarchical design. An EDA (Electronic Design Automation) tool may receive a hierarchical static design and allow the user to instantiate a top level hierarchical rotating pcell using one or more parameters including an angle parameter to indicate a rotation angle. Based on the one or more parameters, the EDA tool may recursively identify, in the user's static hierarchical design, lower level static cells and replace them with the hierarchical rotating pcells based on the angle parameter in the already instantiated upper level hierarchical rotating pcells. The EDA tool may instantiate and re-instantiate hierarchical rotating pcells until leaf-level cells have been reached to dynamically generate an IC (integrated circuit) design with hierarchical rotating pcells from the user's static hierarchical design such that rotation can be accomplished without flattening the IC design.

Systems and methods for dynamically generating hierarchical rotating pcells from a static integrated circuit design

Disclosed herein are embodiments of systems, methods, and products providing technology database independent pcells to be seamlessly customized and implemented in a yet unknown IC package library. In particular, the technology database independent pcells may have a code to execute callback functions to retrieve the package library name of the parent cells hosting the pcells. Based upon the library name, the pcell code may access the technology files stored in the technology database of the package library of the parent cells to retrieve the layer name, layer number, the design resolution, and/or other information such as design rule information of the parent cells hosting the pcells. Based on the layer number, the resolution, and/or other information the pcells can configure for themselves correct layout geometry without any input from a circuit designer.

Technology database independent components for integrated circuit package

Disclosed herein are embodiments of systems, methods, and products that generate two dimensional chains of layout devices, by retrieving the schematic orientation of schematic devices in a symbolic view, and abutting the layout devices based on the schematic orientation such that the two dimensional chains of the layout devices maintain the schematic orientation. More specifically, EDA systems and methods disclosed herein may separate the layout devices into different sets, wherein each set may contain a particular type of layout devices. For example, a first set may contain photonic waveguides and a second set may contain radio frequency (RF) transmission lines. For each set of layout devices, the EDA systems and methods deterministically and iteratively traverse through the layout devices, abutting the devices using the schematic orientation, and creating one or more two dimensional chains of the layout devices.

Methods and systems for schematic driven 2D chaining in an integrated circuit layout

Disclosed are methods, systems, and articles of manufacture for manipulating a hierarchical structure of the electronic design. These techniques identify a set of layout components instantiated from a layout of an electronic design. This set of layout components may constitute, for example, a FigGroup. One or more schematic instances and corresponding schematic connectivity information may be identified from a schematic design of the electronic design, and the one or more schematic instances correspond to the set of layout components. A layout cell or a figure group may be generated for the set of layout components based in part or in whole upon the schematic connectivity information. The original layout may then be transformed into a transformed layout at least by replacing the set of layout components with the generated layout cell or figure group.

Methods, systems, and computer program product for implementing an electronic design by manipulating a hierarchical structure of the electronic design

An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.

Method and system for performing incremental post layout simulation with layout edits

Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.

Methods, systems, and computer program product for implementing virtual prototyping for electronic designs

A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell

Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques identify at least a layout or a portion thereof and determine one or more legal sets of routing tracks for the layout or the portion. One or more figure groups are identified or generated at a first virtual hierarchy, and the one or more first figure groups inherit respective portions of the one or more legal sets of routing tracks. A plurality of legal devices are identified in a layout or a portion thereof, and a figure group is generated at least by determining a boundary for the figure group and enclosing the plurality of layout devices within the boundary. These techniques may modify a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.

Disclosed are methods, systems, and articles of manufacture for dynamically abstracting virtual hierarchies for an electronic design. These techniques identify at least a portion of a layout of an electronic design and a virtual hierarchy in the layout portion according to a value for a display stop level. A plurality of figure groups at one or more virtual hierarchies in the layout portion may also be identified in the layout portion. These techniques select a plurality of layout circuit component designs according to the virtual hierarchy. The layout portion may then be abstracted into an abstracted layout portion at least by displaying the plurality of layout circuit component designs and suppressing one or more remaining layout circuit component designs.

Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design

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Antibes, France

Arnold Ginetti