International Business Machines Corporation

Arnold Flores

Mark D Rogers

Vishal Chittranjan Aslot

Bruce Gerard Mealey

Andre Laurent Albot

Brian Frank Veale

Juan M Casas, Jr

Bret Ronald Olszewski

Jose Eduardo Moreira

Kattamuri Ekanadham

Peter Joseph Heyrman

Debapriya Chatterjee

Gaurav Batra

Jaime A Jaloma

Michael Passaloukos

Tommy Tse

Method, computer program product, and computer system are provided. A first migration of a running logical partition (LPAR) is performed from a first-generation computer to a second-generation computer. Availability of a facility differs between the first- and second-generation computers. Upon completion of the first migration, an operating system of the running LPAR detects whether a required facility in use on the first-generation computer is available on the second-generation computer. Operating system takes an action to continue an orderly execution of the LPAR, the operating system, and threads of an application in the LPAR depending on the availability of the required facility. A second migration is performed of the running LPAR from the second-generation computer back to the first-generation computer. The required facility is available on the first-generation computer. The operating system restores access to threads of the application to the required facility.

Disabling a processor facility on a new processor generation without breaking binary compatibility

In response to encountering a function entry instruction while running an application, a processor computes an entry hash value using a hash of three hash input parameters, wherein one of the input parameters is a secret key stored in the special purpose register. In response to encountering a function exit instruction, the processor computes an exit hash value using the same three input parameters and the same hash used when computing the entry hash value. The processor determines if the entry hash value is the same as the exit hash value. In response to the entry hash value being the same as the exit hash value the processor exits the function and in response to the entry hash value not being the same as the exit hash value the processor executes a trap interrupt.

Comparing hash values computed at function entry and exit for increased security

An embodiment includes issuing an indication that a thread is a time-critical thread. The embodiment initiates an active partition migration, from a source server to a destination server, of a source partition on which the program is stored. The embodiment stores, during the migration, records of locations of pages in memory referenced by the time-critical thread. The embodiment detects that a migration threshold has been reached, indicative of a threshold portion of the migration being complete. Responsive to detecting the migration threshold, the embodiment performs a priority migration of the time-critical thread. The priority migration includes suspending execution of the time-critical thread at the source server, retrieving the records of the locations of the pages in memory referenced by the time-critical thread, and issuing a command to transfer content from the pages to the destination server. The embodiment also includes issuing a migration command to complete the migration.

Partition migration with critical task prioritization

A processor may receive a software fix package. The processor may apply an interim software code fix of the software fix package to software of a device, where the interim software code fix includes adjusting one or more tunable computing parameters to one or more first values. The processor may identify that a reboot of the device is recommended for application of a permanent code fix of the software fix package. The processor may identify that the device was not rebooted after receipt of the software fix package. The processor may determine that a dynamic reconfiguration event has taken place. The processor may apply, automatically, one or more second values for the one or more tunable computing parameters associated with the interim software code fix of the software fix package.

System tuning across live partition migration

During a memory reallocation process, it is determined that a set of memory pages being reallocated are each enabled for a Direct Memory Access (DMA) operation. Prior to writing initial data to the set of memory pages, a pre-access delay is performed concurrently for each memory page in the set of memory pages.

Minimizing delay while migrating direct memory access (DMA) mapped pages

Systems, methods, and computer program products to manage an address translation in a virtually segmented memory system, with included processes comprising a process scoped segment table (STAB) consisting of segment table entries (STEs) that contain effective address segment number (ESID) to system wide unique virtual segment identifier (VSID) mappings, and creating a global kernel segment table (STAB) that itself is translated using a pinned page table entry (PTE). A switch to the global kernel STAB is initiated in response to a page fault interrupt on a process STAB PTE and a PTE reload handler invoked to reload that process STAB PTE. A switch to an original STAB is initiated in order to resume the address translation and resolve the page fault or the interrupt by an operating system executing on the processor.

Virtually addressable hardware global kernel segment table

Methods to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.

Efficient translation reloads for page faults with host accelerator directly accessing process address space without setting up DMA with driver and kernel by process inheriting hardware context from the host accelerator

Systems and computer program products to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.

Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.

Resolving page faults out of context for shared contexts

According to one aspect of the present disclosure a system and technique for refreshing memory topology in virtual machine operating systems is disclosed. The system includes a processor and logic executable by the processor to: responsive to receiving, by an operating system of a virtual machine, a notification of an affinity change relative to workload memory resources, poll a hypervisor for updated memory affinity data; determine, for each logical memory block of the workload memory resources, whether an affinity string for the respective logical memory block has changed; responsive to determining that the affinity string for the respective logical memory block has changed, identify a data structure of the logical memory block maintained by the operating system; and update affinity information in the data structure based on the change to the affinity string of the logical memory block.

Refreshing memory topology in virtual machine operating systems

According to one aspect of the present disclosure, a method and technique for refreshing memory topology in virtual machine operating systems is disclosed. The method includes: responsive to receiving, by an operating system of a virtual machine, a notification of an affinity change relative to workload memory resources, polling a hypervisor for updated memory affinity data; determining, for each logical memory block of the workload memory resources, whether an affinity string for the respective logical memory block has changed; responsive to determining that the affinity string for the respective logical memory block has changed, identifying a data structure of the logical memory block maintained by the operating system; and updating affinity information in the data structure based on the change to the affinity string of the logical memory block.

Growing community of inventors

Round Rock, TX, United States of America

Arnold Flores