Infineon Technologies Austria Ag

Infineon Technologies Ag

Arno Zechmann

Gianmauro Pozzovivo

Robert Illing

Stefan Woehlert

Christian Djelassi

Stefan Krivec

Michael Nelhiebel

Thomas Detzel

Sven Lanzerstorfer

Stefan Decker

Kurt Matoy

Bernhard Auer

Ulrike Fastner

Beate Weissnicht

Annette Sanger

A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.

Semiconductor wafer dicing crack prevention using chip peripheral trenches

A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.

In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.

Semiconductor wafer and method

An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer. The seed includes a noble metal other than gold. The substrate is masked so that a first mask opening is laterally aligned with the first terminal. An unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure in the first mask opening. The mask, the masked portions of the seed layer, and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer.

Method of electrodepositing gold on a copper seed layer to form a gold metallization structure

Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.

Integrated circuit including power transistor cells and a connecting line

Growing community of inventors

Villach, Austria

Arno Zechmann