Atmel Corporation

Sony Corporation

Arm Limited

Arne Aas

Gunnar Gangstoe

Hideyuki Sato

Andreas Onsum

Frode Milch Pedersen

Eivind Holsen

Hakan Lars-Goran Persson

Torgeir Fenheim

Martin Olsson

Odd Jostein Svendsli

Gunnar Gangsto

Runar Sorasen

Terje Saether

Sandeep Kakarlapudi

Mark Underwood

Gunnar Gastoe

Paal Ronny Kastnes

Gunnar Gangstø

Torbjorn Viksand

A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.

Low cost cryptographic accelerator

When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.

Preparing and executing command streams in data processing systems

When executing a program on a data processor comprising an execution unit for executing instructions in a program to be executed by the data processor, the execution unit being associated with one or more hardware units operable to execute instructions, at least one instruction in a program is associated with an indication of whether the instruction should be issued directly for execution by a hardware unit or should be intercepted during its execution by the execution unit. The execution unit then, when decoding the instruction for execution by a hardware unit in the program, determines from the indication associated with the instruction whether the instruction should be issued directly for execution by a hardware unit or intercepted during its execution by the execution unit, and issues the instruction for execution by a hardware unit directly, or pauses execution of the instruction and performs another operation, accordingly.

Control of instruction execution in a data processor

In an embodiment, a circuit comprises: an analog driver operable to drive a sensor voltage on a capacitive sensor; a digital driver; a shield drive control coupled to the analog driver and the digital driver, the shield drive control operable to: during a one or more phases of a capacitive measurement of the capacitive sensor, disable the analog driver and enable the digital driver to drive a driven shield; and during one or more other phases of a capacitive measurement of the capacitive sensor, disable the digital driver and enable the analog driver to drive the driven shield with a driven shield voltage that replicates the sensor voltage.

Driven shield control

A battery management and protection system can include various features to improve safety-critical and other functions. Among the features that can be included in some implementations are automatic loading of safety or other parameters during start-up of the system; a centralized timekeeper and an event system that can trigger actions in the system independently of a central processing unit; use of the same modules for both automatically-controlled safety-related measurements and firmware-controlled measurements; enhanced diagnostic features, and a sleepwalking feature that allows certain modules in the system to continue to perform various functions even when the module or the system is in a low-power sleep mode.

Battery management and protection system using a module in a sleepwalking mode to monitor operational characteristics of a battery

Battery management and protection system using a controller to load safety and configuration parameters into dedicated registers during startup and performing battery protection scans during startup independently of a CPU

A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation.

Method and system for minimizing the accumulated offset error for an analog to digital converter

A compensating DFLL (CDFLL) is disclosed that utilizes temperature readings at regular intervals in combination with production characterization data of a reference oscillator to compensate for frequency drift and nominal frequency error. In some implementations, the CDFLL selects a calibration value that is not optimal for frequency accuracy to minimize accumulated frequency error over time. More particularly, during a calibration run, mismatch between an ideal frequency and an actual frequency is measured, and the measurement is used as a starting point for a next calibration run, such that the accumulated frequency error is averaged almost to zero over time.

Compensating DFLL with error averaging

A microcontroller is disclosed. The microcontroller comprises a processor system and a high voltage interface coupled to the processor system and adapted to be coupled to a battery. The microcontroller further includes a battery management system for monitoring the battery and managing the battery based upon the monitoring of the battery. The microcontroller is a single chip. This one-chip solution saves design cost and PCB space in addition to broadening the functionality of the smart battery application. With the accuracy of the microcontroller, the charge status of the battery can be predicted more accurately and therefore effectively increases actual battery capacity.

Single chip microcontroller including battery management and protection

The subject matter of this specification can be embodied in, among other things, an apparatus that includes a battery system, which includes at least one cell and a charge enable device to couple the at least one cell to a charging voltage. The apparatus also includes an excessive voltage detector to output a signal to control the charge enable device. The signal prevents charging of the at least one cell if an excessive charging voltage is detected based on an activation of a clamping component.

Charge detector

Apparatus, method and computer program product are provided for battery management. In one implementation, a method of communication provided. The method includes enabling determining when a battery pack is coupled to a device, the battery pack including a battery management system. The method also includes generating a random number at the battery management system, the battery management system including battery monitoring circuitry, a processor, memory and a random number generator. The method includes using the random number to provide authentication and if authentication succeeds, enabling communication between the battery pack and the device.

Authenticating a device at a battery pack using a random number generator

A battery pack can include one or more battery cells, current blocking transistors and a battery management system. The disclosed implementations handle over-currents drawn from the battery cells that cause unstable operation of the battery management system. The over-currents are handled without causing an undesired drop in voltage output from the battery cells. The disclosed implementations can handle over-currents even if the over-currents cause the battery management system supply voltage to drop below a minimum operating voltage level for a certain period of time. The disclosed implementations use current blocking transistors that can be configured to block current flow and ensure safe operation of the battery cells in cases where the current drawn from the battery cells would be sufficiently high for a sufficiently long period of time to cause damage to the battery cells.

Growing community of inventors

Trondheim, Norway

Arne Aas