Infineon Technologies Ag

Arndt Gruber

Stephan Schröder

Ralf Schneider

Manfred Pröll

Johann Pfeiffer

Herbert Benzinger

Manfred Proell

Stephan Schroeder

Norbert Wirth

Georg Erhard Eggers

Wolfgang Helfer

Bernhard Ruf

A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment () of a segmented word line not via a first line () otherwise used for deactivation, but rather via a second line () via that the word line segment () is otherwise activated. The second line () can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (), the word line segment can be driven via a switching element (), which couples the word line segment to the second line (), without the complementary switching element () of the driver segment () having to be used for deactivation. It can thereby be ascertained which of two switching elements () of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment ().

Integrated semiconductor memory and method for operating an integrated semiconductor memory

An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells

A method for repairing an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory cells. The first units of memory cells are tested with regard to their functionality. In the case of a defect ascertained in one of the first units, a number of redundant units is programmed as an associated cluster for replacing one or more of the first units. In this way, a repair element is formed with a cluster size corresponding to the number of redundant units. The cluster size of respective repair elements is set in a variable manner by a redundancy circuit. As a result, in a test and repair operation, a comparatively short test time of the memory is made possible in conjunction with a yield that remains good.

Integrated memory and method of repairing an integrated memory

An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

Integrated circuit, test structure and method for testing integrated circuits

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Munich, Germany

Arndt Gruber