Qimonda Ag

Infineon Technologies Ag

Arnd Scholz

Klaus Hummler

Tobias Mono

Lars Dreeskornfeld

Peter Baars

Matthias Goldbach

Wolfgang Roesner

Hans-Peter Moll

Gerhard Enders

Martin Popp

Klaus Muemmler

Christoph Nölscher

Stefan Jakschik

Stefano Parascandola

Werner Graf

Peter Lahnor

Bernd Hintze

Lars Heineck

Stefan Slesazeck

Dirk Caspary

Andrei Josiek

Gouri Sankar Kar

One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Interconnect structure for semiconductor devices

A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.

Methods of manufacturing semiconductor structures

A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Method of manufacturing integrated circuits including a FET with a gate spacer and a fin

An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Integrated circuit and method of manufacturing an integrated circuit

In a process for manufacturing deep trench ( ) memory cells, a method of enhancing the process window by better protecting the nitride spacer ( ) prior to the process of stripping the pad nitride layer ( ). The method also provides for the deposition of a nitride liner ( ) and offers an additional advantage of not requiring the top shoulder ( ) of the nitride spacer ( ) to be over etched during its formation.

Process window enhancement for deep trench spacer conservation

A gate electrode contact spacer ( ) for a vertical DRAM device ( ) and a method for forming the same. Memory cells ( ) are formed within deep trenches ( ) of a workpiece ( ). A temporary spacer adjacent gate electrode contacts ( ) and pad nitride layer are removed. A spacer material is deposited over exposed portions of the workpiece ( ) and over the top and sides of the gate electrode contacts ( ). The spacer material is removed from the horizontal surfaces of the DRAM device ( ), including the exposed portions of the workpiece ( ) and the top of the gate electrode contacts ( ). Spacers ( ) having sidewalls sloping downwardly away from the gate electrode contacts ( ) are left remaining on the gate electrode contact ( ) sides, preventing voids from forming during a subsequent array top oxide deposition. Spacers may also be formed adjacent top regions of isolation trenches simultaneously with the formation of spacers ( ).

Method of forming a gate electrode contact spacer for a vertical DRAM device

A trench top isolation (TTI) layer ( ) and method of forming thereof for a vertical DRAM. A first assist layer ( ) is disposed over trench sidewalls ( ) and trench capacitor top surfaces ( ). A second assist layer ( ) is disposed over the first assist layer ( ). The second assist layer ( ) is removed from over the trench capacitor top surface ( ), and the first assist layer ( ) is removed from the trench capacitor top surface ( ) using the second assist layer ( ) as a mask. The second assist layer ( ) is removed, and a first insulating layer ( ) is disposed over the first assist layer ( ) and trench capacitor top surface ( ). A second insulating layer ( ) is disposed over the first insulating layer ( ), and the second insulating layer ( ) is removed from the trench sidewalls ( ). The first insulating layer ( ) and the first assist layer ( ) are removed from the trench sidewalls ( ). The TTI layer ( ) comprises the first and second insulating layer portions ( ) that are left remaining over the trench capacitors ( ). The TTI layer ( ) has a greater thickness over the trench capacitor inner regions ( ) than over the trench capacitor outer regions ( ).

Spacer assisted trench top isolation for vertical DRAM's

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Dresden, Germany

Arnd Scholz