Nxp B.v.

Stmicroelectronics (Crolles 2) Sas

Stmicroelectronics (Rousset) Sas

Arnaud Pouydebasque

Philippe Coronel

Markus Müller

Benjamin Dumont

Stephanne Denorme

A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.

Process for forming a wire portion in an integrated electronic circuit

The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Manufacturing method for planar independent-gate or gate-all-around transistors

A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Growing community of inventors

Gieres, France

Arnaud Pouydebasque