Bull Sas

Arnaud Gazda

Simon Martiel

Jon Oillarburu

A technique for implementing a quantum circuit is provided, where the quantum circuit includes qubits and operators executed on the qubits. The operators include a sequence of π/4 Pauli rotation gates. A surface code layout includes an arrangement of the quantum circuit on a quantum chip, where the arrangement includes at least a tree with a plurality of subtrees, each rotation gate corresponding to a subtree. The technique includes iteratively generating a directed acyclic graph (DAG) of the quantum circuit, where a front layer of the DAG is a set of rotations that can be effectively implemented at each iteration. The technique includes selecting a subset of the rotations (a 'selected subset') in the front layer in which the subtrees are arranged not to intersect (“non intersecting subsets”).

Compilation technique for surface code architecture

The disclosure refers to method for converting an input quantum circuit comprising gates into an output quantum circuit compliant with execution constraints, comprising: determining if a front layer comprises single-qubit gates, and updating the front layer; reiterating the determining step as long as the front layer comprises single-qubit gates; identifying in the front layer a quantum gate that does not satisfy execution constraints; determining a pattern such that the gate satisfies the execution constraints when applying the adjoint pattern to the gate; adding the pattern to the output quantum circuit, and applying the a joint pattern to the gate; and reiterating these steps until each quantum gate in the input quantum circuit satisfies the execution constraints; wherein each pattern is determined in such a way that a number of CNOT-gates comprised by at least one pattern is minimized.

Method for transforming a quantum circuit while minimizing the CNOT-cost

A method for the development of a compilation process for a quantum circuit on a quantum processor, includes an implementation step of the compilation method including an iteration loop successively including: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor; a step of detecting, in the quantum circuit, ineffective quantum gate(s); a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective; and a retroaction step, by way of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.

Method for development of a compiling process for a quantum circuit on a quantum processor and said method

Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.

Compiling on interconnected qubit subsystems

Examples relate to a quantum computing compiling method that includes ordering quantum gates of a nearest neighbor quantum circuit in function of dependencies between the quantum gates to obtain a quantum gates hierarchical order. The hierarchical order includes a succession of front lines comprising multiple respective quantum gates of the nearest neighbor quantum circuit. The method includes successively selecting, for each front line, and following the hierarchical order, a shuttling for each respective quantum gate of the front line. The shuttling selection is, for each front line, based on a predefined constraint.

Quantum computing compiling

A method for developing a method for compiling a quantum circuit on a quantum processor, comprising:

Growing community of inventors

Versailles, France

Arnaud Gazda